Index: anr/section-2.1.tex
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--- anr/section-2.1.tex	(revision 237)
+++ anr/section-2.1.tex	(revision 247)
@@ -46,64 +46,77 @@
 capacity for complex system implementations.
 This market is in significant expansion and is estimated to 914\,M\$ in 2012.
-The HPC market size is estimated today by FPGA providers at 214\,M\$. 
-Using FPGA limits the NRE costs to the design cost.
-This boosts the developpment of automatic design tools and methodologies.
+%The HPC market size is estimated today by FPGA providers at 214\,M\$. 
+%Using FPGA limits the NRE costs to the design cost.
+%This boosts the developpment of automatic design tools and methodologies.
 %
-%Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, 
-%Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand 
-%for very high performance (HPC) primes over other requirements. They tend to use the highest 
-%performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative 
-%architectures and algorithms. These companies show up in different "traditional" applications and market 
-%segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
-%emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers 
-%at 214\,M\$. 
-%%%
 \parlf
+Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, 
+Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand 
+for very high performance (HPC) primes over other requirements. They tend to use the highest 
+performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative 
+architectures and algorithms. These companies show up in different "traditional" applications and market 
+segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
+emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers 
+at 214\,M\$. 
 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
 of FPGA-based solutions is limited by the lack of design automation.
+\\
 Nowadays, there are neither commercial nor academic tools covering the whole design process
-from the system level specification to the bit stream generation.
-% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
-%              au dessous n'a pas de sens.
-% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
-By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
-parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
-processor,  bus core, ...) as well as incorporate their own IP.
-Designers can then generate a synthesized netlist, simulation test bench and custom
-software library that reflect the hardware configuration.
-%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
-%% IA: ces lignes ont ete verifiees et corrigÃ©e pa \altera. De plus C2H est plutot limite.
-Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
-simulate the platform at a high design level (systemC). 
-In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
-tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
-PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
-coprocessors from a C++ description.
-Nevertheless, they can only deal with data dominated applications and they do not handle
-the platform level.
-Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
-Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
-Designers can design and simulate a system using MATLAB and Simulink. The tool will then
-automatically generate synthesizable Hardware Description Language (HDL) code mapped to
-\xilinx pre-optimized macro-cells.
-However, this tool targets only DSP based algorithms.
-\\
-Consequently, a designer developping an embedded system needs to master four different
-design environments:
-\begin{enumerate}
-  \item a virtual prototyping environment such as SoCLib for system level exploration,
-  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
-  from \xilinx) to define the hardware architecture,
-  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
-        coprocessor synthesis,
-  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
-\end{enumerate}
-Furthermore, mixing these tools requires an important interfacing effort and this makes
-the design process very complex and achievable only by designers skilled in many domains.
+from the system level specification to the bit stream generation neither for embedded system design
+nor for HPC.
+
+%PC => IA et Alain
+%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
+%Je le mets donc en commentaire
+
+%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
+%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
+%processor,  bus core, ...) as well as incorporate their own IP.
+%Designers can then generate a synthesized netlist, simulation test bench and custom
+%software library that reflect the hardware configuration.
+%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
+%simulate the platform at a high design level (systemC). 
+%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
+%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
+%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
+%coprocessors from a C++ description.
+%Nevertheless, they can only deal with data dominated applications and they do not handle
+%the platform level.
+%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
+%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
+%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
+%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
+%\xilinx pre-optimized macro-cells.
+%However, this tool targets only DSP based algorithms.
+%\\
+%Consequently, a designer developping an embedded system needs to master four different
+%design environments:
+%\begin{enumerate}
+%  \item a virtual prototyping environment such as SoCLib for system level exploration,
+%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
+%  from \xilinx) to define the hardware architecture,
+%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
+%        coprocessor synthesis,
+%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
+%\end{enumerate}
+%Furthermore, mixing these tools requires an important interfacing effort and this makes
+%the design process very complex and achievable only by designers skilled in many domains.
+
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
 The aim of the COACH project is to integrate all these design steps into a single design framework
 and to allow \textbf{pure software} developpers to develop embedded systems.
 }\end{minipage}\end{center}
+
+%PC => IA et Alain
+% le paragraphe suivant est coupÃ© collÃ© de la section suivante 2.2
+
+
 \parlf
+The COACH project proposes an open-source framework for mapping multi-tasks software applications
+on Field Programmable Gate Array circuits (FPGA).
+It aims to propose solutions to the societal/economical challenges by
+providing SMEs novel design capabilities enabling them to increase their
+design productivity with design exploration and synthesis methods that are placed on top 
+of the state-of-the-art methods.
 We believe that the combination of a design environment dedicated to software developpers
 and FPGA targets,
