Index: /anr/section-2.1.tex
===================================================================
--- /anr/section-2.1.tex	(revision 246)
+++ /anr/section-2.1.tex	(revision 247)
@@ -46,64 +46,77 @@
 capacity for complex system implementations.
 This market is in significant expansion and is estimated to 914\,M\$ in 2012.
-The HPC market size is estimated today by FPGA providers at 214\,M\$. 
-Using FPGA limits the NRE costs to the design cost.
-This boosts the developpment of automatic design tools and methodologies.
+%The HPC market size is estimated today by FPGA providers at 214\,M\$. 
+%Using FPGA limits the NRE costs to the design cost.
+%This boosts the developpment of automatic design tools and methodologies.
 %
-%Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, 
-%Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand 
-%for very high performance (HPC) primes over other requirements. They tend to use the highest 
-%performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative 
-%architectures and algorithms. These companies show up in different "traditional" applications and market 
-%segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
-%emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers 
-%at 214\,M\$. 
-%%%
 \parlf
+Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, 
+Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand 
+for very high performance (HPC) primes over other requirements. They tend to use the highest 
+performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative 
+architectures and algorithms. These companies show up in different "traditional" applications and market 
+segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
+emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers 
+at 214\,M\$. 
 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
 of FPGA-based solutions is limited by the lack of design automation.
+\\
 Nowadays, there are neither commercial nor academic tools covering the whole design process
-from the system level specification to the bit stream generation.
-% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
-%              au dessous n'a pas de sens.
-% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
-By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
-parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
-processor,  bus core, ...) as well as incorporate their own IP.
-Designers can then generate a synthesized netlist, simulation test bench and custom
-software library that reflect the hardware configuration.
-%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
-%% IA: ces lignes ont ete verifiees et corrigée pa \altera. De plus C2H est plutot limite.
-Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
-simulate the platform at a high design level (systemC). 
-In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
-tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
-PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
-coprocessors from a C++ description.
-Nevertheless, they can only deal with data dominated applications and they do not handle
-the platform level.
-Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
-Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
-Designers can design and simulate a system using MATLAB and Simulink. The tool will then
-automatically generate synthesizable Hardware Description Language (HDL) code mapped to
-\xilinx pre-optimized macro-cells.
-However, this tool targets only DSP based algorithms.
-\\
-Consequently, a designer developping an embedded system needs to master four different
-design environments:
-\begin{enumerate}
-  \item a virtual prototyping environment such as SoCLib for system level exploration,
-  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
-  from \xilinx) to define the hardware architecture,
-  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
-        coprocessor synthesis,
-  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
-\end{enumerate}
-Furthermore, mixing these tools requires an important interfacing effort and this makes
-the design process very complex and achievable only by designers skilled in many domains.
+from the system level specification to the bit stream generation neither for embedded system design
+nor for HPC.
+
+%PC => IA et Alain
+%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
+%Je le mets donc en commentaire
+
+%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
+%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
+%processor,  bus core, ...) as well as incorporate their own IP.
+%Designers can then generate a synthesized netlist, simulation test bench and custom
+%software library that reflect the hardware configuration.
+%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
+%simulate the platform at a high design level (systemC). 
+%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
+%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
+%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
+%coprocessors from a C++ description.
+%Nevertheless, they can only deal with data dominated applications and they do not handle
+%the platform level.
+%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
+%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
+%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
+%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
+%\xilinx pre-optimized macro-cells.
+%However, this tool targets only DSP based algorithms.
+%\\
+%Consequently, a designer developping an embedded system needs to master four different
+%design environments:
+%\begin{enumerate}
+%  \item a virtual prototyping environment such as SoCLib for system level exploration,
+%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
+%  from \xilinx) to define the hardware architecture,
+%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
+%        coprocessor synthesis,
+%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
+%\end{enumerate}
+%Furthermore, mixing these tools requires an important interfacing effort and this makes
+%the design process very complex and achievable only by designers skilled in many domains.
+
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
 The aim of the COACH project is to integrate all these design steps into a single design framework
 and to allow \textbf{pure software} developpers to develop embedded systems.
 }\end{minipage}\end{center}
+
+%PC => IA et Alain
+% le paragraphe suivant est coupé collé de la section suivante 2.2
+
+
 \parlf
+The COACH project proposes an open-source framework for mapping multi-tasks software applications
+on Field Programmable Gate Array circuits (FPGA).
+It aims to propose solutions to the societal/economical challenges by
+providing SMEs novel design capabilities enabling them to increase their
+design productivity with design exploration and synthesis methods that are placed on top 
+of the state-of-the-art methods.
 We believe that the combination of a design environment dedicated to software developpers
 and FPGA targets,
Index: /anr/section-2.2.tex
===================================================================
--- /anr/section-2.2.tex	(revision 246)
+++ /anr/section-2.2.tex	(revision 247)
@@ -1,10 +1,15 @@
 % Relevance of the proposal 
-The COACH proposal addresses directly the \emph{Embedded Systems} item of
-the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
-providing SMEs novel design capabilities enabling them to increase their
-design productivity with design exploration and synthesis methods that are placed on top 
-of the state-of-the-art methods.
-This project proposes an open-source framework for mapping multi-tasks software applications
-on Field Programmable Gate Array circuits (FPGA).
+%The COACH proposal addresses directly the \emph{Embedded Systems} item of
+%the ARPEGE program. 
+
+%PC => IA et ALain
+%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1
+
+%It aims to propose solutions to the societal/economical challenges by
+%providing SMEs novel design capabilities enabling them to increase their
+%design productivity with design exploration and synthesis methods that are placed on top 
+%of the state-of-the-art methods.
+%This project proposes an open-source framework for mapping multi-tasks software applications
+%on Field Programmable Gate Array circuits (FPGA).
 %%%
 \parlf
@@ -56,8 +61,9 @@
     silicon density and power efficiency, able to adapt its computing
     structure to computation patterns that can be speed-up and/or
-    power efficient.  The ROMA project study a pipeline of
-    evolved low-power coarse grain reconfigurable operators to avoid
-    traditional overhead, in reconfigurable devices, related to the
-    interconnection network.  The project will borrow from the ROMA
+    power efficient.  %The ROMA project study a pipeline of
+    %evolved low-power coarse grain reconfigurable operators to avoid
+    %traditional overhead, in reconfigurable devices, related to the
+    %interconnection network.  
+	The project will borrow from the ROMA
     ANR project and the ongoing joint INRIA-STMicro
     Nano2012 project to adapt existing pattern extraction algorithms
@@ -90,5 +96,5 @@
   \item
     Regarding system level architecture, the project is based on the know-how
-    acquired by the \upmc and \tima laboratories in the framework of various projects  
+    acquired by \upmc and \tima in the framework of various projects  
     in the field of communication architectures for shared memory multi-processors systems
     (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
@@ -109,5 +115,5 @@
     parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb}, 
     process construction \cite{Feau:96} and memory management \cite{bee}
-    will be very useful as a front-end for the a high-level synthesis tools.
+    will be very useful as a front-end for HLS tools.
 \end{itemize}
 %%%
@@ -120,5 +126,5 @@
 Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design 
 constraints and objectives (real-time, low-power). It will permit designing  complex SoC 
-based on IP cores (memory, peripherals, network controllers, communication processors), 
+based on IP cores (memory, peripherals...), 
 running Embedded Software, as well as an Operating System with associated middleware and 
 API and using hardware accelerator automatically generated. It will also permit to use 
Index: /anr/section-3.1.tex
===================================================================
--- /anr/section-3.1.tex	(revision 246)
+++ /anr/section-3.1.tex	(revision 247)
@@ -79,4 +79,36 @@
 In addition, \xilinx System Generator and SOPC Builder are closed world
 since each one imposes their own IPs which are not interchangeable.
+%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
+%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
+%processor,  bus core, ...) as well as incorporate their own IP.
+%Designers can then generate a synthesized netlist, simulation test bench and custom
+%software library that reflect the hardware configuration.
+%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
+%simulate the platform at a high design level (systemC). 
+%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
+%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
+%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
+%coprocessors from a C++ description.
+%Nevertheless, they can only deal with data dominated applications and they do not handle
+%the platform level.
+%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
+%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
+%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
+%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
+%\xilinx pre-optimized macro-cells.
+%However, this tool targets only DSP based algorithms.
+%\\
+%Consequently, a designer developping an embedded system needs to master four different
+%design environments:
+%\begin{enumerate}
+%  \item a virtual prototyping environment such as SoCLib for system level exploration,
+%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
+%  from \xilinx) to define the hardware architecture,
+%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
+%        coprocessor synthesis,
+%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
+%\end{enumerate}
+%Furthermore, mixing these tools requires an important interfacing effort and this makes
+%the design process very complex and achievable only by designers skilled in many domains.
 
 \subsubsection{High Level Synthesis}