Index: /anr/section-3.2.tex
===================================================================
--- /anr/section-3.2.tex	(revision 23)
+++ /anr/section-3.2.tex	(revision 24)
@@ -3,5 +3,5 @@
 (accelerating solutions for existing software applications) and embedded
 applications (implementing an application on a low power standalone
-device).  The design steps are presented figure~\ref{flow}.
+device).  The design steps are presented figure~\ref{coach-flow}.
 \begin{figure}[hbtp]\leavevmode\center
   \includegraphics[width=.8\linewidth]{flow}
Index: /anr/task-2.tex
===================================================================
--- /anr/task-2.tex	(revision 23)
+++ /anr/task-2.tex	(revision 24)
@@ -7,5 +7,5 @@
 \begin{objectif}
 This task relies to the prototyping and the generation of FPGA-SoC digital systems.
-Its is described on figure~\ref{arci-csg} and it consists of
+Its is described on figure~\ref{archi-csg} and it consists of
 Its objective is to allows the system designer to explore the system space design by quickly prototyping and then to generate automatically the FPGA-SoC system.
 This task consists of