Index: /anr/section-4.1.tex
===================================================================
--- /anr/section-4.1.tex	(revision 254)
+++ /anr/section-4.1.tex	(revision 255)
@@ -29,5 +29,5 @@
 For generating the coprocessor of a task mapped as hardware, \verb+CSG+
 controls the HAS tools described below.
-From these inputs \verb!CSG! can generate the entire system (both software \&
+From these inputs \verb!CSG! can generate the entire system (both software and
 hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
@@ -80,5 +80,5 @@
     dominated description.
     This task contains also the development of a frequency adaptator
-    that will allow the coprocessors to respect the processor \& the bus
+    that will allow the coprocessors to respect the processor and the bus
     frequency.
 \item[Task-6: \textit{PC/FPGA communication middleware}]