- Timestamp:
- Feb 18, 2010, 8:27:00 AM (15 years ago)
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anr/task-6.tex
r231 r257 31 31 \end{livrable} 32 32 33 \subtask The objective of this sub-task is to specify the application and todevelop the34 high level code . The application isin the domain of surveillance of critical33 \subtask In this sub-task, \TRT will specify and develop the 34 high level code of an application in the domain of surveillance of critical 35 35 infrastructures. 36 36 The objective is to detect and classify the presence of humans in the restricted area. 37 The algorithm is based on the work of Viola and Jones\cite{thales-viola}.37 The algorithm we will use is based on the work of Viola and Jones\cite{thales-viola}. 38 38 It implements in particular a cascade of classifiers operating on Haar like features, 39 39 where simple weak classifiers at the beginning of the cascade reject a majority of … … 69 69 70 70 \subtask 71 In this task, \TRT will evaluate the COACH platform. In particular, \TRT will verify71 In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify 72 72 its ability to generate a whole VHDL of an embedded system on FPGA for an application 73 73 mixing control and data flow aspects. \TRT will evaluate the performance of the … … 88 88 \end{livrable} 89 89 90 \subtask FLEXRAS proposes a SoC architecture integrating an embedded FPGA (eFPGA). 90 \subtask FLEXRAS will design an application based on MPEG-2 video standard. 91 FLEXRAS will propose a SoC architecture integrating an embedded FPGA (eFPGA). 91 92 The architecture is composed essentially of a processor, a bus and several RAMs. 92 93 The embedded FPGA is connected to the bus and communicates with the other components. … … 119 120 \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0} 120 121 \zied will propose to test COACH framework and the \zied architecture template 121 throught a basic application.122 throught an application based on MPEG-2. 122 123 This applicattion will containt 3 communicating tasks under the COACH format specified 123 124 in {\novers{\specGenManual}} deliverable. … … 139 140 The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly 140 141 coupled module between ARM processor and FPGA. 142 For the COACH project, \navtel will automatically synthetize two cores: one for software radio 143 through a polyphase resampler and one for an industrial control application through an embedded 144 PID controller. 145 The objective is to sequence the cores in realtime in FPGA using partial configuration methods. 146 This will allow us to gain experience on automatic multi core sequencing at system level. The 147 specification for our first work package will concern this aspect. 148 141 149 The ESC can function on different topologies: Single, parallel or Grid computing modes for 142 150 industrial and scientific applications.
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