Index: /anr/task-6.tex
===================================================================
--- /anr/task-6.tex	(revision 256)
+++ /anr/task-6.tex	(revision 257)
@@ -31,9 +31,9 @@
     \end{livrable}
 
-  \subtask The objective of this sub-task is to specify the application and to develop the
-    high level code. The application is in the domain of surveillance of critical
+  \subtask In this sub-task, \TRT will specify and develop the
+    high level code of an application in the domain of surveillance of critical
     infrastructures.
     The objective is to detect and classify the presence of humans in the restricted area.
-    The algorithm is based on the work of Viola and Jones\cite{thales-viola}.
+    The algorithm we will use is based on the work of Viola and Jones\cite{thales-viola}.
     It implements in particular a cascade of classifiers operating on Haar like features,
     where simple weak classifiers at the beginning of the cascade reject a majority of
@@ -69,5 +69,5 @@
 
   \subtask 
-    In this task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
+    In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
     its ability to generate a whole VHDL of an embedded system on FPGA for an application
     mixing control and data flow aspects. \TRT will evaluate the performance of the
@@ -88,5 +88,6 @@
     \end{livrable}
 
-  \subtask FLEXRAS proposes a SoC architecture integrating an embedded FPGA (eFPGA).
+  \subtask FLEXRAS will design an application based on MPEG-2 video standard. 
+  	FLEXRAS will propose a SoC architecture integrating an embedded FPGA (eFPGA).
     The architecture is composed essentially of a processor, a bus and several RAMs.
     The embedded FPGA is connected to the bus and communicates with the other components.
@@ -119,5 +120,5 @@
       \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0}
         \zied will propose to test COACH framework and the \zied architecture template
-        throught a basic application.
+        throught an application based on MPEG-2.
         This applicattion will containt 3 communicating tasks under the COACH format specified
         in {\novers{\specGenManual}} deliverable.
@@ -139,4 +140,11 @@
   The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly
   coupled module between ARM processor and FPGA.
+  For the COACH project, \navtel will automatically synthetize two cores: one for software radio 
+  through a polyphase resampler and one for an industrial control application through an embedded 
+  PID controller.
+  The objective is to sequence the cores in realtime in FPGA using partial configuration methods. 
+  This will allow us to gain experience on automatic multi core sequencing at system level. The 
+  specification for our first work package will concern this aspect. 
+
   The ESC can function on different topologies: Single, parallel or Grid computing modes for
   industrial and scientific applications.