Changeset 260

Timestamp:

Feb 18, 2010, 8:41:31 AM (14 years ago)

Author:

coach

Message:

UBS

File:

• anr/task-6.tex (modified) (2 diffs)

anr/task-6.tex

@@ -139 +139 @@
   \subtask
   The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly
-  coupled module between ARM processor and FPGA.
-  For the COACH project, \navtel will automatically synthetize two cores: one for software radio 
+  coupled module between %ARM 
+  a embedded processor and an FPGA both on a board.
+  By using the COACH environment, \navtel will automatically synthetize two cores: one for software radio 
   through a polyphase resampler and one for an industrial control application through an embedded 
   PID controller.
-  The objective is to sequence the cores in realtime in FPGA using partial configuration methods. 
+  The objective is to sequence the cores in realtime in FPGA using partial configuration methods 
+  proposed in the COACH project. 
   This will allow us to gain experience on automatic multi core sequencing at system level. The 
   specification for our first work package will concern this aspect. 
@@ -149 +151 @@
   The ESC can function on different topologies: Single, parallel or Grid computing modes for
   industrial and scientific applications.
-  The ARM and FPGA configuration also facilitate the co-simulation which allows to  gain
+  %The ARM
+  The processor and FPGA configuration also facilitate the co-simulation which allows to  gain
   time on the development and integration phase.
   The architecture consists of a wrapper that encapsules computing units depending on the