Index: /anr/section-6.1.tex
===================================================================
--- /anr/section-6.1.tex	(revision 266)
+++ /anr/section-6.1.tex	(revision 267)
@@ -47,5 +47,5 @@
 of associated transformation, compilation and synthesis tools, and the
 exploration of the interaction between algorithms and architectures.
-CAIRN is a joint team with CNRS, INSA of Rennes, University of Rennes 1 and ENS Cachan.
+CAIRN is a joint team with CNRS, University of Rennes 1 and ENS Cachan.
 
 \subsubsection{\lip/Compsys}
Index: /anr/task-0.tex
===================================================================
--- /anr/task-0.tex	(revision 266)
+++ /anr/task-0.tex	(revision 267)
@@ -39,4 +39,5 @@
     \begin{livrable}
       \itemL{0}{36}{}{\Supmc}{\upmc management}{1:1:1} Project management at the partner level.
+      \CoutHorsD{0}{36}{\Stima}{project management}{1:1:1}
     \end{livrable}
   \subtask This \ST consists firstly in the building, and next in the administration and the 
@@ -51,5 +52,4 @@
         infrastructure (adding \& suppressing account, retrieving forgotten passwords,
         creation and closing development branch, ...)
-      \CoutHorsD{0}{36}{\Stima}{project management}{1:1:1}
       \CoutHorsD{0}{36}{\Slip}{project management}{1:1:1}
     \end{livrable}
Index: /anr/task-3.tex
===================================================================
--- /anr/task-3.tex	(revision 266)
+++ /anr/task-3.tex	(revision 267)
@@ -49,5 +49,5 @@
 	  { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
 	  already available from \altera}
-      \itemV{12}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
+      \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
       \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0}
Index: /anr/task-4.tex
===================================================================
--- /anr/task-4.tex	(revision 266)
+++ /anr/task-4.tex	(revision 267)
@@ -71,5 +71,5 @@
         The high level specification tools, such as GAUT, have to be able to use synthesis feed-back
         informations in order to explore the design space and to generate optimized architectures.
-    \itemL{24}{36}{x}{\Subs}{Micro-architecture Exploration}{0:0:8}
+    \itemL{24}{36}{x}{\Subs}{Micro-architecture Exploration}{0:4:4}
         Release of the GAUT software that supports the features defined in \MAE
     \end{livrable}
Index: /anr/task-7.tex
===================================================================
--- /anr/task-7.tex	(revision 266)
+++ /anr/task-7.tex	(revision 267)
@@ -67,9 +67,9 @@
     They will be published on the public WEB site.
    \begin{livrable}
-   \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:0:1}
+   \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:1:0}
         This user manual shows how to generate a complete HW/SW system by using CSG tool.
-    \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:0:1}
+    \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:1:0}
         This user manual shows how to apply loop transformations to a task.
-    \itemL{18}{24}{d}{\Sirisa}{ASIP user manual}{0:1:1}
+    \itemL{18}{36}{d}{\Sirisa}{ASIP user manual}{0:1:1}
         This user manual shows how to customize a processor to obtain an ASIP.
     \itemL{18}{24}{d}{\Subs}{HLS user manual}{0:1:0}