Index: /anr/coach_summary.txt =================================================================== --- /anr/coach_summary.txt (revision 271) +++ /anr/coach_summary.txt (revision 272) @@ -1,68 +1,36 @@ -The objective of COACH is to provide an integrated design flow, based on the -SoCLib virtual prototyping infrastructure, and optimized for the design of -multi-processors digital systems targeting FPGA devices. -Such digital systems are generally integrated -into one or several chips, and there are two types of applications: -They can be embedded (autonomous) applications -such as personal digital assistants (PDA), ambiant computing components, -or wireless sensor networks (WSN). -They can also be extension boards connected to a PC to accelerate a specific computation, -as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). +The objective of COACH is to provide an integrated design flow, based on the SoCLib virtual prototyping infrastructure, and optimized for the design of multi-processors digital systems targeting FPGA devices. Such digital systems are generally integrated into one or several chips, and there are two types of applications: +- They can be embedded (autonomous) applications such as personal digital assistants (PDA), ambiant computing components, or wireless sensor networks (WSN). +- They can also be extension boards connected to a PC to accelerate a specific computation, as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). The COACH project will provide three hardware architectural templates: - - A Neutral architectural template based on the SoCLib IP core library and the - VCI/OCP communication infrastructure. - - An Altera architectural template based on the Altera IP core library, the - AVALON system bus and the NIOS processor. - - A Xilinx architectural template based on the Xilinx IP core library, the PLB - system bus and the Microblaze processor. + - A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure. + - An Altera architectural template based on the Altera IP core library, the AVALON system bus and the NIOS processor. + - A Xilinx architectural template based on the Xilinx IP core library, the PLB system bus and the Microblaze processor. -The COACH design flow will be dedicated to system designers, and will as -much as possible hide the hardware characteristics to the end-user. -The specification of the application will be independant from the -architectural template and the target FPGA device. +The COACH design flow will be dedicated to system designers, and will as much as possible hide the hardware characteristics to the end-user. The specification of the application will be independant from the architectural template and the target FPGA device. -To reach this ambitious goal, the project will rely on the experience and the -complementariness of partners in the following domains: -- Operating system and communication middleware (Tima, Lip6), -- MPSoC architectures (Tima, Lab-Sticc, Lip6), -- ASIP architectures (Inria/Cairn), -- High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip). +To reach this ambitious goal, the project will rely on the experience and the complementariness of partners in the following domains: +- Operating system and communication middleware (Tima, Lip6) +- MPSoC architectures (Tima, Lab-Sticc, Lip6) +- ASIP architectures (Inria/Cairn) +- High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip) -The COACH project does not start from scratch. -It stronly relies on the SoCLib virtual prototyping platform for prototyping, -(DSX, component library), operating systems (MUTEKH, DNA/OS). -It also leverages on several existing technologies: the GAUT and UGH tools for HLS, -the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations -and on the Xilinx and Altera IP core libraries. -Finally it will use the Xilinx and Altera logic and physical synthesis -tools to generate the FPGA configuration bitstreams. +The COACH project does not start from scratch. It stronly relies on the SoCLib virtual prototyping platform for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS). It also leverages on several existing technologies: the GAUT and UGH tools for HLS, the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations, and the Xilinx and Altera IP core libraries. Finally it will use the Xilinx and Altera logic and physical synthesis tools to generate the FPGA configuration bitstreams. -Two major FPGA companies are involved in the project: Xilinx will contribute -as a contractual partner providing documentation and manpower; Altera will contribute as -a supporter, providing documentation and development boards. These two companies are strongly motivated -to help the COACH project to generate efficient bitsreams for both FPGA families. -The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide -real use cases to benchmark the COACH design environment and to analyze the designer productivity -improvements. +Two major FPGA companies are involved in the project: Xilinx will contribute as a contractual partner providing documentation and manpower; Altera will contribute as a supporter, providing documentation and development boards. These two companies are strongly motivated to help the COACH project to generate efficient bitsreams for both FPGA families. -Following the general policy of the SoCLib platform, the COACH project will be an open -infrastructure, available in the framework of the SoCLib server. -The architectural templates, and the COACH software tools will be distributed under the -GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib -IP core library) will be freely available for non commercial use. For industrial exploitation -the technology providers are ready to propose commercial licenses, directly to the end user, -or through a third party. +The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide real use cases to benchmark the COACH design environment and to evaluate the designer productivity improvements. -Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the -"letters of interest", that have collected during the preparation of the project : -- ADACSYS -- MDS -- INPIXAL -- CAMKA System -- ATEME -- ALSIM -- SILICOMP-AQL -- ABOUND Logic -- EADS-ASTRIUM +Following the general policy of the SoCLib platform, the COACH project will be an open infrastructure, available in the framework of the SoCLib server. The architectural templates, and the COACH software tools will be distributed under the GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib IP core library) will be freely available for non commercial use. For industrial exploitation the technology providers are ready to propose commercial licenses, directly to the end user, or through a third party. + +Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the "letters of interest", that have collected during the preparation of the project : + - ADACSYS + - MDS + - INPIXAL + - CAMKA System + - ATEME + - ALSIM + - SILICOMP-AQL + - ABOUND Logic + - EADS-ASTRIUM Index: /anr/coach_summary_fr.txt =================================================================== --- /anr/coach_summary_fr.txt (revision 271) +++ /anr/coach_summary_fr.txt (revision 272) @@ -1,71 +1,39 @@ -L'objectif du projet COACH est de fournir un environnement complet de conception de -systèmes digitaux multi-processeurs qui cible les circuits FPGA. -Cet environnement sera basé sur la plate-forme SocLib de prototypage virtuel. -Ces systèmes digitaux sont en général intégrés dans un ou plusieurs circuits -et il y a principalement deux types d'applications: -des applications autonomes comme celles embarquées dans des PDA, des composants -domotiques ou des réseaux de capteurs; -des cartes d'extension connectées à un PC pour du calcul haute performance -(HPC) ou du traitement de signal haute performance (HSSP). +L'objectif du projet COACH est de fournir un environnement complet de conception de systèmes numériques multi-processeurs qui cible les circuits FPGA. Cet environnement sera basé sur la plate-forme SocLib de prototypage virtuel. Ces systèmes numériques sont en général intégrés dans un ou plusieurs circuits et il y a principalement deux types d'applications: + - des applications autonomes comme celles embarquées dans des PDA, des composants domotiques ou des réseaux de capteurs; + - des cartes d'extension connectées à un PC pour du calcul haute performance (HPC) ou du traitement de signal haute performance (HSSP). Le projet COACH fournira trois patrons architecturaux. - - Le patron architectural neutre qui sera basé sur la bibliotèque d'IP cores de + - Le patron architectural neutre qui sera basé sur la bibliothèque d'IP cores de SocLib et sur l'infrastructure de communication VCI/OCP. VCI/OCP communication infrastructure. - - Le patron architectural Altera qui sera basé sur la bibliotèque d'IP cores d'Altera, + - Le patron architectural Altera qui sera basé sur la bibliothèque d'IP cores d'Altera, le bus AVALON et le processeur NIOS. - - Le patron architectural Xilinx qui sera basé sur la bibliotèque d'IP cores de Xilinx, + - Le patron architectural Xilinx qui sera basé sur la bibliothèque d'IP cores de Xilinx, le bus PLB et le processeur Microblaze. -L'environnement de conception COACH sera conçu pour être utilisable pas un -concepteur système. Pour cela il masquera aux utilisateurs les -caractéristiques matérielles fines. De plus les descriptions des applications seront -toalement indépendante des patrons architecturaux ainsi que du circuit FPGA visé. +L'environnement de conception COACH sera conçu pour être utilisable pas un concepteur système. Pour cela il masquera aux utilisateurs les caractéristiques matérielles fines. De plus les descriptions des applications seront totalement indépendante des patrons architecturaux ainsi que du circuit FPGA visé. -Pour atteindre ces objectifs ambitieux, le projet repose sur la -complémentarité et l'expérience des partenaires dans les domaines suivants: - - système d'exploitation et middleware de communication (Tima, Lip6), - - architectures MPSoC (Tima, Lab-Sticc, Lip6), - - architectures ASIP (Inria/Cairn), - - synthèse de haut niveau (Tima, Lab-Sticc, Lip6), et compilation (Ens-Lyon/Lip). +Pour atteindre ces objectifs ambitieux, le projet repose sur la complémentarité et l'expérience des partenaires dans les domaines suivants: + - système d'exploitation et middleware de communication (Tima, Lip6), + - architectures MPSoC (Tima, Lab-Sticc, Lip6), + - architectures ASIP (Inria/Cairn), + - synthèse de haut niveau (Tima, Lab-Sticc, Lip6), et compilation (Ens-Lyon/Lip). -Le projet COACH ne demarre pas de rien mais s'appuie fortement sur la -plate-forme SocLib (DSX, bibliotèque de composants), sur les systèmes -d'exploitation (MUTEKH, DNA/OS). -Il tirera également profit de plusieurs outils existants: les outils UGH et GAUT pour la -synthèse de haut niveau, le projet ROMA pour les processeurs à instructions -spécifiques (ASIP), les outils SYNTOL et BEE pour les transformations et -l'analyse au niveau source, les bibliotèques de composants d'Altera et Xilinx. -Enfin il utilisera les outils de synthèse logique et physique d'Altera et de -Xilinx pour générer les bitstreams de configuration des FPGA. +Le projet COACH ne démarre pas de rien mais s'appuie fortement sur la plate-forme SocLib (DSX, bibliothèque de composants), sur les systèmes d'exploitation (MUTEKH, DNA/OS). Il tirera également profit de plusieurs outils existants: les outils UGH et GAUT pour la synthèse de haut niveau, le projet ROMA pour les processeurs à instructions spécifiques (ASIP), les outils SYNTOL et BEE pour les transformations et l'analyse au niveau source, les bibliothèques de composants d'Altera et Xilinx. Enfin il utilisera les outils de synthèse logique et physique d'Altera et de Xilinx pour générer les bitstreams de configuration des FPGA. -Les deux plus grandes sociétés du domaine des FPGA prennent part à -ce projet. Xilinx est partenaire du projet et fournira des ressources humaines -et de la documentation. Altera supportera le projet en fournissant de la -documentation et des cartes de développement. -Ces deux sociétés sont très motivées à aider ce projet pour générer des -bitstreams optimisés pour leurs circuits FPGA. -Le rôle des partenaires industriels Bull, Thales, Navtel and Flexras est de -fournir des applications industrielles pour évaluer les performances de -l'environnement COACH ainsi que mesurer les gains de productivité obtenus. +Les deux plus grandes sociétés du domaine des FPGA sont impliquées dans le projet. Xilinx est partenaire du projet. Altera contribue au projet en fournissant au projet de la documentation et des cartes de développement. Ces deux sociétés sont très motivées à aider ce projet pour générer des bitstreams optimisés pour leurs circuits FPGA. -Conformément à la politique générale de la plate-forme SocLib, le projet COACH -sera sous licence libre, et disponible sur le serveur de la plate-forme SocLib. -Les patrons architecturaux et les logiciels seront distribués sous la licence -GPL, les modèles en VHDL synthétisable des composants du patron architectural -neutre seront distribués aussi librement mais leur utilisation sera restreinte -à un usage non commercial. Pour une utilisation commerciale de ces composants, -les concepteurs de ces modèles fourniront des licences commerciales soit directement -à l'utilisateur final soit à un tiers. +Le rôle des partenaires industriels Bull, Thales, Navtel and Flexras est de fournir des applications industrielles pour évaluer les performances de l'environnement COACH ainsi que mesurer les gains de productivité obtenus. -Finalement, le projet COACH est supporté par un grand nombre de PME comme le -que le montre les lettres de soutien qui ont été collectées. -- ADACSYS -- MDS -- INPIXAL -- CAMKA System -- ATEME -- ALSIM -- SILICOMP-AQL -- ABOUND Logic -- EADS-ASTRIUM +Conformément à la politique générale de la plate-forme SocLib, le projet COACH sera sous licence libre, et disponible sur le serveur de la plate-forme SocLib. Les patrons architecturaux et les logiciels seront distribués sous la licence GPL, les modèles en VHDL synthétisable des composants du patron architectural neutre seront distribués aussi librement mais leur utilisation sera restreinte à un usage non commercial. Pour une utilisation commerciale de ces composants, les concepteurs de ces modèles fourniront des licences commerciales soit directement à l'utilisateur final soit à une tierce partie. + +Finalement, le projet COACH est soutenu par un grand nombre de PME comme le montrent les lettres d'intérêt qui ont été collectées: + - ADACSYS + - MDS + - INPIXAL + - CAMKA System + - ATEME + - ALSIM + - SILICOMP-AQL + - ABOUND Logic + - EADS-ASTRIUM Index: /anr/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 271) +++ /anr/section-3.2.tex (revision 272) @@ -44,43 +44,39 @@ \begin{description} \item[\textit{Design Space Exploration by Virtual Prototyping}]: - The COACH environment will allow to easily map a parallel application described as a process - network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will - permit to explore the design space by allowing system designer to select and - parameterize the target architecture, and to define the best hardware/software - partitioning of the application. -\item[\textit{High-Level Synthesis}]: - COACH will allow the automatic generation of hardware accelerators when required + The COACH environment will allow to easily map a parallel application (formally described as + an abstract network of process and communication channels) + COACH will permit the system designer to explore the design space, and to define the best + hardware/software partitioning of the application. +\item[\textit{Integration of system level modeling and HLS tools}]: + COACH will support the automated generation of hardware accelerators when required by using High-Level Synthesis (HLS) tools. These HLS tools will be fully integrated into a complete system-level design environment. Moreover, COACH will support both data and control dominated applications, - and the HLS tools of COACH will support a common language and coding style + and the HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer. - COACH will provide a tool which will automatically explore the micro-architectural + COACH will provide a tool which will automatically explore the micro-architectural design space of coprocessor. \item[\textit{High-level code transformation}]: - COACH will allow to optimize the memory usage, to enhance the parallelism through + COACH will allow to optimize the memory usage, to enhance the parallelism through loop transformations and parallelization. The challenge is to identify the coarse grained parallelism and to generate, from a sequential algorithm, application containing multiple communicating - tasks. To this aim, one may adapt techniques which were developed in the 1990 for + tasks. COACH will adapt techniques which were developed in the 1990 for the construction of distributed programs. However, in the context of HLS, there are - still several original problems to be solved, mainly to do with the construction of - FIFO communication channels and with memory optimization. - Additionnal preprocessing, source-level transformations, are thus - required to improve the process. - Particularly, this includes parallelism exposure and efficient memory mapping. + several original problems to be solved, related to the FIFO communication channels and with + memory optimization. COACH will support code transformation by providing a source to source C2C tool. -\item[\textit{Hardware/Software communication middleware}]: - COACH will implement an homogeneous HW/SW communication infrastructure and - communication APIs (Application Programming Interface), that will be used for - communications between software tasks running on embedded processors and - dedicated hardware coprocessors. This will allow explore the design space by - mapping the tasks of the application (described as a process network) on a - shared-memory, MPSoC architecture. +\item[\textit{Unified Hardware/Software communication middleware}]: + COACH will rely on he SoCLib experience to implement an unified hardware/software communication + infrastructure and communication APIs (Application Programming Interface), to support + communications between software tasks running on embedded processors and dedicated + hardware coprocessors. The main issue here is to support easy migration + from a software implementation to an hardware implementation. \item[\textit{Processor customization}]: -ASIP design will be addressed by the COACH project. COACH will allow system designers to explore -the various level of interactions between the original CPU micro-architecture and its - extension. It will also allow to retarget the compiler instruction-selection pass. Finally, - COACH will integrate ASIP design in a complete System-level design framework. + ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. + COACH will allow system designers to explore the various level of interactions between + the original CPU micro-architecture and its extension. It will also allow to retarget + the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis + in a complete System-level design framework. \end{description} Index: /anr/section-6.2.tex =================================================================== --- /anr/section-6.2.tex (revision 271) +++ /anr/section-6.2.tex (revision 272) @@ -1,12 +1,12 @@ -The COACH project will be coordinated by professor Alain Greiner from +The Coach project will be coordinated by the Professor Alain Greiner from Université Pierre et Marie Curie. Alain Greiner is the initiator and the main architect of the SoCLib project. -This ANR platform for virtual prototyping of MPSoCs involved 6 industrial companies -(including ST Microelectronics and \thales) and ten academic laboratories -(5 of them are involved in the COACH project). -The SoCLib project was managed by \thales, but the technical coordination has been done -by Alain Greiner, who has a good experience in coordinating large technical projects +This ANR plat-form for virtual prototyping of MPSoCs involved 6 industrial companies +(including ST Microelectronics and Thales) and ten academic laboratories +(5 of them are involved in the Coach project). +The SoCLib project was managed by Thales, but the technical coordination has been done +by Alain Greiner, that has a good experience in coordinating large technical projects in both industrial and academic contexts: -% + \begin {itemize} \item @@ -16,9 +16,8 @@ From 1986 to 1990, he worked for the french BULL company, as team leader, in charge of designing the Basic Processing Unit for the BULL -DPS7000 computer, the most powerfull mainframe of the family. +DPS7000 computer, the most powerfull mainframe from the family. \item In 1990, Alain Greiner joined UPMC, as Professor and became the head of the -MASI laboratory in 1994. From 2000, he was head of the Hardware Department -of the LIP6 laboratory. +MASI laboratory in 1994. \item From 1990 to 2000, he was the leader of the the ALLIANCE project: This GPL based @@ -26,4 +25,7 @@ in more than 200 universities worlwide, for education and research. This project obtained the Seymour Cray award in 1994. +\item +From 2000 to 2009, he was the head of the Hardware Department +of the LIP6 laboratory, and associate-director of the LIP6 laboratory. \end {itemize}