Index: anr/section-3.2.tex
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--- anr/section-3.2.tex	(revision 269)
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@@ -44,43 +44,39 @@
 \begin{description}
 \item[\textit{Design Space Exploration by Virtual Prototyping}]:
-    The COACH environment will allow to easily map a parallel application described as a process 
-	network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
-	permit to explore the design space by allowing system designer to select and 
-	parameterize the target architecture, and to define the best hardware/software 
-	partitioning of the application.
-\item[\textit{High-Level Synthesis}]:
-    COACH will allow the automatic generation of hardware accelerators when required
+        The COACH environment will allow to easily map a parallel application (formally described as
+        an abstract network of process and communication channels)  
+	COACH will permit the system designer to explore the design space, and to define the best 
+        hardware/software partitioning of the application.
+\item[\textit{Integration of system level modeling and HLS tools}]:
+        COACH will support the automated generation of hardware accelerators when required
 	by using High-Level Synthesis (HLS) tools. These HLS tools will be
 	fully integrated into a complete system-level design environment.
  	Moreover, COACH will support both data and control dominated applications,
-    and the HLS tools of COACH will support a common language and coding style 
+        and the HLS tools of COACH will support a common language and coding style 
 	to avoid re-engineering by the designer.
-    COACH will provide a tool which will automatically explore the micro-architectural 
+        COACH will provide a tool which will automatically explore the micro-architectural 
 	design space of coprocessor.
 \item[\textit{High-level code transformation}]:
-    COACH will allow to optimize the memory usage, to enhance the parallelism through 
+        COACH will allow to optimize the memory usage, to enhance the parallelism through 
 	loop transformations and parallelization. The challenge is to identify the coarse 
 	grained parallelism and to generate,
 	from a sequential algorithm, application containing multiple communicating
-	tasks. To this aim, one may adapt techniques which were developed in the 1990 for 
+	tasks. COACH will adapt techniques which were developed in the 1990 for 
 	the construction of distributed programs. However, in the context of HLS, there are 
-	still several original problems to be solved, mainly to do with the construction of 
-	FIFO communication channels and with memory optimization.
-	Additionnal preprocessing, source-level transformations, are thus
-	required to improve the process.
-	Particularly, this includes parallelism exposure and efficient memory mapping.
+	several original problems to be solved, related to the  FIFO communication channels and with 
+        memory optimization. 
 	COACH will support code transformation by providing a source to source C2C tool.
-\item[\textit{Hardware/Software communication middleware}]:
-    COACH will implement an homogeneous HW/SW communication infrastructure and
-    communication APIs (Application Programming Interface), that will be used for 
-    communications between software tasks running on embedded processors and 
-    dedicated hardware coprocessors. This will allow explore the design space by 
-	mapping the tasks of the application (described as a process network) on a 
-	shared-memory, MPSoC architecture.
+\item[\textit{Unified Hardware/Software communication middleware}]:
+        COACH will rely on he SoCLib experience to implement an unified hardware/software communication 
+        infrastructure and communication APIs (Application Programming Interface), to support  
+        communications between software tasks running on embedded processors and dedicated 
+        hardware coprocessors. The main issue here is to support easy migration 
+        from a software implementation to an hardware implementation.
 \item[\textit{Processor customization}]:
-ASIP design will be addressed by the COACH project. COACH will allow system designers to explore 
-the various level of interactions between the original CPU micro-architecture and its
-  extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
- COACH will integrate ASIP design in a complete System-level design framework.
+        ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. 
+        COACH will allow system designers to explore the various level of interactions between 
+        the original CPU micro-architecture and its extension. It will also allow to retarget 
+        the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
+        in a complete System-level design framework.
 \end{description}
 
