Index: /anr/coach_global.txt =================================================================== --- /anr/coach_global.txt (revision 273) +++ /anr/coach_global.txt (revision 273) @@ -0,0 +1,142 @@ + +The market of digital systems is about 4,600 M\$ today and is estimated to +5,600 M\$ in 2012. However the ever growing applications complexity involves +integration of heterogeneous technologies and requires the design of +complex Multi-Processors System on Chip (MPSoC). + +During the last decade, the design of ASICs (Application Specific +Integrated Circuits) appeared to be more and more reserved to high volume markets, because +the design and fabrication costs of such components exploded, due to increasing NRE (Non +Recurring-Engineering) costs. +Fortunately, FPGA (Field Programmable Gate Array) components, such as the +Virtex5 family from Xilinx or the Stratix4 family from Altera, can nowadays +implement a complete MPSoC with multiple processors and several dedicated +coprocessors for a few Keuros per device. Many applications are initially captured +algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest +in tools that can provide an implementation path directly from HLLs to hardware. +Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, +Co-design, High-Level Synthesis...) are now mature and allow the automation of +a system-level design flow. Unfortunately, ESL tool development to date has primarily focused +on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). +However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design +methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting +designs written in C/C++ language and implementing the function straight into FPGA. +We believe that coupling FPGA technologies and ESL methodologies +will allow both SMEs (Small and Medium Enterprise) and +major companies to design innovative devices and to enter new, low and +medium volume markets. + +The objective of COACH is to provide an integrated design flow, based on the +SoCLib infrastructure~\cite{soclib}, and optimized for the design of +multi-processors digital systems targeting FPGA devices. +Such digital systems are generally integrated +into one or several chips, and there are two types of applications: +They can be embedded (autonomous) applications +such as personal digital assistants (PDA), ambiant computing components, +or wireless sensor networks (WSN). +They can also be extension boards connected to a PC to accelerate a specific computation, +as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). + +The COACH environment will integrate several hardware and software technologies: + +Design Space Exploration: + The COACH environment will allow to describe an application as a process + network i.e. a set of tasks communicating through FIFO channels. + COACH will allow to map the application on a shared-memory, MPSoC architecture. + It will permit to easily explore the design space to help the system designer + to define the proper hardware/software partitioning of the application. + For each point in the design space, metrics such as throughput, latency, power + consumption, silicon area, memory allocation and data locality will be provided. + These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure + and high-level estimation methodologies. + +Hardware Accelerators Synthesis (HAS): + COACH will allow the automatic generation of hardware accelerators when required. + Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor + (ASIP) design environment and source-level transformation tools (loop transformations + and memory optimisation) will be provided. + This will allow further exploration of the micro-architectural design space. + HLS tools are sensitive to the coding style of the input specification and the domain + they target (control vs. data dominated). + The HLS tools of COACH will support a common language and coding style to avoid + re-engineering by the designer. + +Platform based design: + COACH will handle both Altera and Xilinx FPGA devices. + COACH will define architectural templates that can be customized by adding + dedicated coprocessors and ASIPs and by fixing template parameters such as + the number of embedded processors, the number of sizes of embedded memory banks + or the embedded the operating system. + However, the specification of the application will be independant of both the + architectural template and the target FPGA device. + Basically, the following three architectural templates will be provided: + - A Neutral architectural template based on the SoCLib IP core library and the + VCI/OCP communication infrastructure. + - An Altera architectural template based on the Altera IP core library, the + AVALON system bus and the NIOS processor. + - A Xilinx architectural template based on the Xilinx IP core library, the PLB + system bus and the Microblaze processor. + +Hardware/Software communication middleware: + COACH will implement an homogeneous HW/SW communication infrastructure and + communication APIs (Application Programming Interface), that will be used for + communications between software tasks running on embedded processors and + dedicated hardware coprocessors. + +The COACH design flow will be dedicated to system designers, and will as +much as possible hide the hardware characteristics to the end-user. + +To reach this ambitious goal, the project will rely on the experience and the +complementariness of partners in the following domains: +Operating system and communication middleware (Tima, Lip6), +MPSoC architectures (Tima, Lab-Sticc, Lip6), +ASIP architectures (Inria/Cairn), +High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip). + +The COACH project does not start from scratch. +It stronly relies on the SoCLib virtual prototyping platform for prototyping, +(DSX, component library), operating systems (MUTEKH, DNA/OS). +It also leverages on several existing technologies: +on the GAUT and UGH tools for HLS, +on the ROMA project for ASIP, +on the SYNTOL and BEE tools for source-level analysis and transformations +and on the Xilinx and Altera IP core libraries. +Finally it will use the Xilinx and Altera logic and physical synthesis +tools to generate the FPGA configuration bitstreams. + +The COACH proposal has been prepared during one year by a technical working group +involving the 5 academic partners (one monthly meeting from january 2009 to february +2010). The objective was to analyse the issues of integrating +and enhancing the existing tools and tecnnologies into a unique framework. +Most of the general software architecture of the proposed design flow (including the +exchange format specification) has been define by this working group. +Because the COACH project leanes on the ANR SoCLib platform, it may be described as an +extension of the SoCLib platform. + +Two major FPGA companies are involved in the project: Xilinx will contribute +as a contractual partner providing documentation and manpower; Altera will contribute as +a supporter, providing documentation and development boards. These two companies are strongly motivated +to help the COACH project to generate efficient bitsreams for both FPGA families. +The role of the industrial partners \bull, \thales, \navtel and \zied is to provide +real use cases to benchmark the COACH design environment and to analyze the designer productivity +improvements. + +Following the general policy of the SoCLib platform, the COACH project will be an open +infrastructure, available in the framework of the SoCLib server. +The architectural templates, and the COACH software tools will be distributed under the +GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib +IP core library) will be freely available for non commercial use. For industrial exploitation +the technology providers are ready to propose commercial licenses, directly to the end user, +or through a third party. + +Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the +"letters of interest", that have collected during the preparation of the project : +- ADACSYS +- MDS +- INPIXAL +- CAMKA System +- ATEME +- ALSIM +- SILICOMP-AQL +- ABOUND Logic +- EADS-ASTRIUM Index: /anr/coach_objectifs.txt =================================================================== --- /anr/coach_objectifs.txt (revision 273) +++ /anr/coach_objectifs.txt (revision 273) @@ -0,0 +1,30 @@ + +Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry. Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) is not an option for SMEs (Small and Medium Enterprises). Fortunately, the new FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete multi-processor architecture on a single device. But the design of embedded system is a long and complex task that requires expertise in software, software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling. Only very few SMEs have these multiple expertises and are present on the embedded system market. + +The major objective of COACH is to provide to SMEs an open-source framework to design embedded systems on FPGA devices. This framework will be dedicated to system-level designer. + +The second objective of COACH is HPC. In HPC (High Performance Computing), the targeted application is running on a PC. The COACH framework will help the system designer to accelerate an HPC applcation by migrating critical parts into a SoC embedded into an FPGA device plugged to the PC PCI/X bus. This will allow SMEs to enter HPC market for applications that cannot be accelerated by he current GPU based solutions. + +To reach these objectives, the key scientific and technical issues are : + +1) Design Space Exploration by Virtual Prototyping + +The COACH environment will allow to easily map a parallel application (described as an abstract process network Model of Computation) on a shared-memory, MPSoC architecture. COACH will permit the system designer to explore the design space, and to define the best hardware/software partitioning of the application. + +2) Integration of system-level modeling and HLS tools + +COACH will support the automated generation of hardware accelerators when required by using High-Level Synthesis (HLS) tools. These HLS tools will be fully integrated into the system-level design environment. Moreover, COACH will support both data and control dominated applications, and the HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer. + +3) High-level code transformation + +COACH will allow to optimize the memory usage, to enhance the parallelism through loop transformations and parallelization. The challenge is to identify the coarse grained parallelism and to generate, from a sequential algorithm, applications containing multiple communicating tasks. Coach will adapt techniques which were developed in the 1990 for the construction of distributed programs. However, in the context of HLS, there are several original problems to be solved, related to the FIFO communication channels and with memory optimization. COACH will support code transformation by providing a source to source C2C tool. + +4) Unified Hardware/Software communication middleware + +COACH will rely on he SoCLib experience to implement an unified hardware/software communication infrastructure and communication APIs (Application Programming Interface), to support communications between software tasks running on embedded processors and dedicated hardware coprocessors. The main issue here is to support easy migration +from a software implementation to an hardware implementation. + +5) Processor customization + +ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. COACH will allow system designers to explore the various level of interactions between the original CPU micro-architecture and its extension. It will also allow to retarget the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis in a complete System-level design framework. + Index: /anr/coach_retombees.txt =================================================================== --- /anr/coach_retombees.txt (revision 273) +++ /anr/coach_retombees.txt (revision 273) @@ -0,0 +1,15 @@ + +Today, FPGAs become important actors in the computational domain that was originally dominated by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed on a per-application basis. For many applications, FPGAs offer significant performance benefits over microprocessors implementation. There is still a performance degradation of one order of magnitude versus an equivalent ASIC implementations, but low cost (500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive choice for low-to-medium volume applications. + +Since their introduction in the mid eighties, FPGAs evolved from a simple, low-capacity gate array to devices (Altera STRATIX III, xilinx Virtex V) that provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement complex systems like multi-processors platform with application dedicated coprocessors. This market is in significant expansion and is estimated to 914 M$ in 2012. + +Nowadays, there are no commercial or academic tools covering the whole design flow from the system level specification to the bitstream generation neither for embedded system design nor for HPC. + +The COACH project proposes an open-source framework for mapping multi-tasks software applications on Field Programmable Gate Array circuits (FPGA). It aims to propose solutions to the societal/economical challenges by providing SMEs novel design capabilities enabling them to increase their design productivity with design exploration and synthesis methods that are placed on top of the state-of-the-art methods. + +We believe that the combination of a design environment dedicated to software developpers and FPGA targets, will allow small and even very small companies to propose embedded system and accelerating solutions for standard software applications with attractive and competitive prices. This new market may explode in the same way as the micro-computer market in the eighties, whose success was due to the low cost of the first micro-processors (compared to main frames) and the advent of high level programming languages which allowed a high number of programmers to launch start-ups in software engineering. + +The large number of SMEs that have expressed interest for the COACH project (ten letters of interest collected +in one month) demonstrates that theres is a real need for this type of tools. + +The COACH project can have a strong economical impact. Index: /anr/coach_tasks.txt =================================================================== --- /anr/coach_tasks.txt (revision 273) +++ /anr/coach_tasks.txt (revision 273) @@ -0,0 +1,38 @@ + + +The project is split into 8 tasks described in short below: + +T1) Project management + +This task relates to the monitoring of the COACH project. It includes a monthy meeting of the steering committee. + +T2) Backbone + +This task tackles the fundamental points of the project that are the defintion of the COACH inputs and outputs, the inter-tools exchange formats, the three supported architectural templates, the hardware/software communication middleware, and the general design flow. This task contains also the development of the associated tools. + +T3) System generation + +This task addresses the virtual prototyping and the generation of the final bitstream (including hardware and +embedded software). + +T4) Hardware accelerator synthesis front-end + +This task mainly focusses on four functionalities: optimization of the memory usage, parallelism enhancement through loop transformations, coarse grain parallelization and ASIP generation. + +T5) Hardware accelerator synthesis back-end + +This task groups two functionalities: High-Level Synthesis of data dominated coprocessors and High Level Synthesis of control dominated coprocessors. It contains also the development of a a generic retiming mechanism +to adapt the coprocessors to the system frequency. + +T6) PC/FPGA communication middleware + +This task is mainly dedicated to HPC. Subtasks are mainly the partitioning evaluation tool, the software drivers for both PC and FPGA-SoC sides, the hardware communication components and the support for dynamic partial reconfiguration. + +T7) Industrial demonstrators + +This task groups the demonstrators of the COACH project. Most subtasks are industrial applications that will be used to evaluate the COACH framework. Another subtask is to evaluate the interfacing between the COACH framework and a proprietary system-level design tool (Thales). A third subtask is to evaluate the COACH framework on a third embedded FPGA architecture (Flexras). + +T8) Dissemination + +This task is related to the dissemination of the project results. It mainly consists of the production of the 4 COACH releases and the publication on the WEB server, the production of tutorials and user manuals, the publication of research papers in international journals and conferences and the organization of workshops and tutorials in international conferences. +