Index: /anr/architecture-csg.fig =================================================================== --- /anr/architecture-csg.fig (revision 274) +++ /anr/architecture-csg.fig (revision 275) @@ -46,7 +46,7 @@ 6 6165 3240 8100 4325 6 6528 3544 7697 4325 -4 1 0 50 -1 2 13 0.0000 4 148 1142 7106 3722 architecture\001 -4 1 0 50 -1 2 13 0.0000 4 202 658 7146 4228 library\001 -4 1 0 50 -1 2 13 0.0000 4 202 820 7106 3968 template\001 +4 1 0 50 -1 2 13 0.0000 4 150 1080 7106 3722 architecture\001 +4 1 0 50 -1 2 13 0.0000 4 195 630 7146 4228 library\001 +4 1 0 50 -1 2 13 0.0000 4 195 795 7106 3968 template\001 -6 1 1 1 2 0 7 50 -1 -1 4.000 1 0.0000 7133 3370 927 87 7133 3370 8060 3370 @@ -77,9 +77,31 @@ 4 1 0 50 -1 2 14 0.0000 4 225 735 6285 2745 library\001 -6 +6 9135 180 10485 4005 +6 9225 1035 10395 1755 +2 4 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5 + 10365 1730 10365 1055 9240 1055 9240 1730 10365 1730 +4 1 0 50 -1 2 14 0.0000 4 165 1005 9810 1580 bitstream\001 +4 1 0 50 -1 2 14 0.0000 4 165 660 9810 1340 FPGA\001 +-6 +6 9225 180 10395 945 +2 4 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5 + 10365 900 10365 225 9240 225 9240 900 10365 900 +4 1 0 50 -1 2 14 0.0000 4 165 240 9810 495 IP\001 +4 1 0 50 -1 0 12 0.0000 4 195 1005 9810 720 (IP-XACT)\001 +-6 +6 9180 1935 10350 2475 +2 4 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5 + 10335 2425 10335 1975 9210 1975 9210 2425 10335 2425 +4 1 0 50 -1 2 14 0.0000 4 165 1005 9795 2245 simulator\001 +-6 +2 1 1 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2 + 0 0 2.00 120.00 240.00 + 9767 2445 9767 3345 +4 1 0 50 -1 2 14 0.0000 4 225 1320 9810 3605 performance\001 +4 1 0 50 -1 2 14 0.0000 4 225 825 9810 3905 analysis\001 +-6 2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2 0 0 2.00 120.00 240.00 2932 1922 3912 1922 -2 4 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5 - 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The design steps are presented figure~\ref{coach-flow}. +\ADDED{ +The end-user input is +either a HPC application (an application running on a PC that must be accelarate), +or an embedded application (a standalone application), +or a function of a larger design.} \begin{figure}[hbtp]\leavevmode\center \includegraphics[width=.8\linewidth]{flow} @@ -13,16 +18,27 @@ COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. The user input will consist of a process network describing the coarse grain parallelism -of the application, an instance of a generic hardware platform -and a mapping of processes on the platform components. +of the application, an instance of an architectural template +and a mapping of processes on the architectural template components. COACH will offer different targets to map the processes: software (the process runs as a software task on a SoC processor), ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), and hardware (the process is implemented as a synthesized hardware coprocessor). -\item[Application compilation:] Once the SoC architecture is validated through performances -analysis, COACH will generate automatically an executable containing the host application and +\item[Application compilation:] +\begin{SUPPRESSEDENV} +Once the SoC architecture is validated through performances analysis, +COACH will generate automatically an executable containing the host application and the FPGA bitstream. This bitstream contains both the hardware architecture and the SoC application software. The user will be able to launch the application by loading the bitstream on an FPGA and running the executable on PC. +\end{SUPPRESSEDENV}\begin{ADDEDENV} +Once the SoC architecture is validated through performances analysis, +COACH generates its bitstream in the case of HPC or embedded application, +or its IP-XACT description for its integration in the case of a function. +Both descriptions contain the hardware architecture and the application software. +Furthermore in the HPC case, an executable containing the host application is +also generated and the user will be able to launch the application by loading +the bitstream on an FPGA and running the executable on PC. +\end{ADDEDENV} \end{description} Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 274) +++ /anr/section-4.1.tex (revision 275) @@ -11,5 +11,4 @@ \caption{\label{archi-hpc} Software architecture of HPC} \end{figure} -%FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ? % Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} @@ -30,9 +29,17 @@ controls the HAS tools described below. From these inputs \verb!CSG! can generate the entire system (both software and -hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the +hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger +design or} +as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the FPGA device\footnote{Additional partial bitstreams are generated in case of dynamic partial reconfiguration}. + \begin{ADDEDENV} + \\ + Furthermore the architecture template and hardware component libraries will be described + under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other + architecture or the enhancement of existing template with IP. + \end{ADDEDENV}% \parlf The software architecture for HAS is presented in figure~\ref{archi-hls}.