Index: /anr/section-3.2.tex
===================================================================
--- /anr/section-3.2.tex	(revision 276)
+++ /anr/section-3.2.tex	(revision 277)
@@ -5,5 +5,5 @@
 either a HPC application (an application running on a PC that must be accelarate),
 or an embedded application (a standalone application),
-or a function of a larger design.}
+or a sub-system application of a larger design.}
 \begin{figure}[hbtp]\leavevmode\center
   \includegraphics[width=.8\linewidth]{flow}
@@ -35,5 +35,5 @@
 Once the SoC architecture is validated through performances analysis,
 COACH generates its bitstream in the case of HPC or embedded application,
-or its IP-XACT description for its integration in the case of a function.
+or its IP-XACT description for its integration in the case of a sub-system application.
 Both descriptions contain the hardware architecture and the application software.
 Furthermore in the HPC case, an executable containing the host application is
Index: /anr/section-4.1.tex
===================================================================
--- /anr/section-4.1.tex	(revision 276)
+++ /anr/section-4.1.tex	(revision 277)
@@ -31,5 +31,5 @@
 hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger
 design or}
-as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
+as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
 launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the