Index: anr/task-5.tex
===================================================================
--- anr/task-5.tex	(revision 237)
+++ anr/task-5.tex	(revision 278)
@@ -20,6 +20,6 @@
 \item Implementing the communication scheme at all levels: partition help, software
 implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
-\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
-to optimize FPGA ressource usage.
+%\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
+%to optimize FPGA ressource usage.
 \end{itemize}
 
@@ -33,7 +33,7 @@
 %
 \begin{workpackage}
-  \subtask
+  \subtask{Implementation of API between PC and FPGA-SoC}
     This \ST deals with the COACH HPC feature that consists in accelerating an existing
-    apllication running on a PC by migrating critical parts into a SoC implemented on an
+    application running on a PC by migrating critical parts into a SoC implemented on an
     FPGA plugged to the PC PCI/X bus.
     The main steps and components of this \ST are:
@@ -54,31 +54,33 @@
         \setMacroInAuxFile{hpcCommHelper}
         A library implementing the communication API defined in the {\hpcCommApi} deliverable.
-        This library is dedicated to help the end-user to partition an applicattion for
-        HPC.
+        This library is dedicated to help the end-user to partition an application for HPC.
       \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0}
         \setMacroInAuxFile{hpcCommLinux}
-        The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
-        library and probably a LINUX module.
-      \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
-        \setMacroInAuxFile{hpcMutekDriver}
-        The FPGA-SoC part of the communication API, a driver.
+        The PC part of the HPC communication API that communicates with the FPGA-SOC, a
+        library and a LINUX module.
+%      \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
+%        \setMacroInAuxFile{hpcMutekDriver}
+%        The FPGA-SoC part of the communication API, a driver.
       \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
         \setMacroInAuxFile{hpcDnaDriver}
-        Port of the {\hpcMutekDriver} driver on the DNA OS.
-      \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
-        Bug corrections and enhancements of communication middleware
-        (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
-        \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
+        The FPGA-SoC part of the communication API.
+%        Port of the {\hpcMutekDriver} driver on the DNA OS.
+%      \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
+%        Bug corrections and enhancements of communication middleware
+%        (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
+%        \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
     \end{livrable}
 
-\subtask This \ST deals with the implementation of hardware and SystemC modules
+\subtask{SystemC model of the PCI/X}
+    This \ST deals with the implementation of hardware and SystemC modules
     required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
-    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
-        \setMacroInAuxFile{hpcPlbBridge}
-        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
-    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
-        \setMacroInAuxFile{hpcAvalonBridge}
-        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
+% FIXME: moved to task 3 (CSG)
+%    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
+%        \setMacroInAuxFile{hpcPlbBridge}
+%        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
+%    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
+%        \setMacroInAuxFile{hpcAvalonBridge}
+%        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
     \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
         The SystemC description of a component that generates PCI/X traffic. It is
@@ -86,34 +88,34 @@
     \end{livrable}
 
-\subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
-It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
-    \begin{livrable}
-    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
-        Modification of the CSG software to support statically reconfigurable tasks.
-    \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
-		This livrable is a CSG module allowing to partition the task graph along
-		the dynamic partial reconfiguration regions. The resulting task-region assignement
-		is directly used for generation of bitstreams. The module also produces reconfiguration
-		management software to be run on the SoC-FPGA.
-    \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
-        \setMacroInAuxFile{hpcDynconfDriver}
-	    The drivers required by the DNA OS in order to manage dynamic partial
-        reconfiguration inside the SoC-FPGA.
-    \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
-        Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
-    \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
-        Extension of the HPC partionning helper in order to integrate dynamic partial
-        reconfiguration dedicated features (reconfiguration time of regions, variable
-        number of coprocessors).
-    \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
-        \xilinx will work with \tima in order to better take into account during
-        partitioning decisions specific constraints due to partial reconfiguration process.
-        The deliverable is a document describing the \xilinx specific constraints.
-    \end{livrable}
-%\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
-%   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
-%   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
-%   \begin{livrable}
-%   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
-%   \end{livrable}
+% \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
+% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
+%     \begin{livrable}
+%     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
+%         Modification of the CSG software to support statically reconfigurable tasks.
+%     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
+% 		This livrable is a CSG module allowing to partition the task graph along
+% 		the dynamic partial reconfiguration regions. The resulting task-region assignement
+% 		is directly used for generation of bitstreams. The module also produces reconfiguration
+% 		management software to be run on the SoC-FPGA.
+%     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
+%         \setMacroInAuxFile{hpcDynconfDriver}
+% 	    The drivers required by the DNA OS in order to manage dynamic partial
+%         reconfiguration inside the SoC-FPGA.
+%     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
+%         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
+%     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
+%         Extension of the HPC partionning helper in order to integrate dynamic partial
+%         reconfiguration dedicated features (reconfiguration time of regions, variable
+%         number of coprocessors).
+%     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
+%         \xilinx will work with \tima in order to better take into account during
+%         partitioning decisions specific constraints due to partial reconfiguration process.
+%         The deliverable is a document describing the \xilinx specific constraints.
+%     \end{livrable}
+% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
+% %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
+% %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
+% %   \begin{livrable}
+% %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
+% %   \end{livrable}
 \end{workpackage}
