Index: /anr/Makefile =================================================================== --- /anr/Makefile (revision 277) +++ /anr/Makefile (revision 278) @@ -1,5 +1,5 @@ # set here all the sources files # required to build anr.pdf -SOURCES= anr.tex anr.bib section-1.tex \ +SOURCES= anr.tex anr.bib anr.sty section-1.tex \ section-2.tex section-2.1.tex section-2.2.tex \ flow.pdf section-3.1.tex section-3.2.tex \ @@ -12,15 +12,13 @@ section-6.1.tex section-6.2.tex section-7.tex -TABLES= table_upmc_full.tex table_upmc_short.tex \ - table_tima_full.tex table_tima_short.tex \ +TABLES= \ table_inria_cairn_full.tex table_inria_cairn_short.tex \ table_inria_compsys_full.tex table_inria_compsys_short.tex \ + table_tima_full.tex table_tima_short.tex \ table_ubs_full.tex table_ubs_short.tex \ - table_xilinx_full.tex table_xilinx_short.tex \ + table_upmc_full.tex table_upmc_short.tex \ table_bull_full.tex table_bull_short.tex \ table_thales_full.tex table_thales_short.tex \ - table_zied_full.tex table_zied_short.tex \ - table_navtel_full.tex table_navtel_short.tex \ - table_livrable_01.tex table_livrable_02.tex + table_mds_full.tex table_mds_short.tex # PROGRAMS @@ -31,5 +29,6 @@ @$(FIG2DEV) -L pdf -p aaa $< $@ -anr.pdf: $(SOURCES) gantt1.tex gantt2.tex gantt $(TABLES) +anr.pdf: $(SOURCES) gantt + touch gantt1.tex gantt2.tex $(TABLES) @echo "Generating pdf file" @pdflatex anr.tex || true @@ -40,9 +39,4 @@ @grep ndefine anr.log -anr.bbl:anr.aux anr.bib - bibtex anr || true - -anr.aux gantt1.tex gantt2.tex $(TABLES): - touch $@ gantt: gantt.l Index: /anr/anr.sty =================================================================== --- /anr/anr.sty (revision 277) +++ /anr/anr.sty (revision 278) @@ -85,9 +85,7 @@ \let\UBS\disable% \let\UPMC\disable% -\let\XILINX\disable% \let\BULL\disable% \let\THALES\disable% -\let\NAVTEL\disable% -\let\ZIED\disable% +\let\MDS\disable% }{% \ifx\ALL\enable% @@ -97,9 +95,7 @@ \ifx\TIMA\disable\let\TIMA\enable\fi% \ifx\UBS\disable\let\UBS\enable\fi% - \ifx\XILINX\disable\let\XILINX\enable\fi% \ifx\BULL\disable\let\BULL\enable\fi% \ifx\THALES\disable\let\THALES\enable\fi% - \ifx\NAVTEL\disable\let\NAVTEL\enable\fi% - \ifx\ZIED\disable\let\ZIED\enable\fi% + \ifx\MDS\disable\let\MDS\enable\fi% \fi% \def\@leader{\begin{small}\textcolor{red}{lead.}\end{small}} @@ -110,12 +106,10 @@ \def\@TIMA{\ifx\TIMA\disable{}\else\ifx\TIMA\enable{\@partner}\else{\@leader}\fi\fi}% \def\@UBS{\ifx\UBS\disable{}\else\ifx\UBS\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@XILINX{\ifx\XILINX\disable{}\else\ifx\XILINX\enable{\@partner}\else{\@leader}\fi\fi}% \def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{\@partner}\else{\@leader}\fi\fi}% \def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@NAVTEL{\ifx\NAVTEL\disable{}\else\ifx\NAVTEL\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@ZIED{\ifx\ZIED\disable{}\else\ifx\ZIED\enable{\@partner}\else{\@leader}\fi\fi}% -\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|}\hline -\Sirisa & \Slip & \Stima & \Subs & \Supmc & \Sxilinx & \Sbull & \Sthales & \Snavtel & \Szied \\\hline -\@IRISA & \@LIP & \@TIMA & \@UBS & \@UPMC & \@XILINX & \@BULL & \@THALES & \@NAVTEL & \@ZIED \\\hline +\def\@MDS{\ifx\MDS\disable{}\else\ifx\MDS\enable{\@partner}\else{\@leader}\fi\fi}% +\begin{tabular}{|c|c|c|c|c|c|c|c|}\hline +\Sirisa & \Slip & \Stima & \Subs & \Supmc & \Smds & \Sbull & \Sthales \\\hline +\@IRISA & \@LIP & \@TIMA & \@UBS & \@UPMC & \@MDS & \@BULL & \@THALES \\\hline \end{tabular}\par } @@ -136,8 +130,8 @@ \begin{description}% %\let\itemsave\item% - \def\subtask{% + \def\subtask##1{% \global\advance\subtaskcnt1 \def\subtaskname{S\taskname-\the\subtaskcnt}% - \item[\subtaskname]}} + \item[\subtaskname: ##1]\mbox{}\\}} {\end{description}} @@ -152,9 +146,8 @@ \let\upmc\relax \let\Supmc\relax \let\altera\relax \let\Saltera\relax - \let\xilinx\relax \let\Sxilinx\relax \let\bull\relax \let\Sbull\relax \let\thales\relax \let\Sthales\relax - \let\zied\relax \let\Szied\relax - \let\navtel\relax \let\Snavtel\relax + \let\mds\relax \let\Smds\relax + \let\xilinx\relax \immediate\write\ganttdata{% T=\the\taskcnt\space S=\the\subtaskcnt\space% @@ -240,9 +233,7 @@ \let\upmc\relax \let\Supmc\relax \let\altera\relax \let\Saltera\relax - \let\xilinx\relax \let\Sxilinx\relax \let\bull\relax \let\Sbull\relax \let\thales\relax \let\Sthales\relax - \let\zied\relax \let\Szied\relax - \let\navtel\relax \let\Snavtel\relax + \let\mds\relax \let\Smds\relax \immediate\write\ganttdata{% T=\the\taskcnt\space S=\the\subtaskcnt\space% Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 277) +++ /anr/anr.tex (revision 278) @@ -65,4 +65,5 @@ \def\zied{FLEXRAS\xspace} \def\Szied{\Sformat{FLEX}\xspace} \def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace} +\def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace} \def\alllabs{\irisa \citi \lip \tima \ubs \upmc} @@ -407,4 +408,6 @@ \bibliography{anr} +\end{document} + \newpage \section{Letters of interest} Index: /anr/flow.fig =================================================================== --- /anr/flow.fig (revision 277) +++ /anr/flow.fig (revision 278) @@ -20,8 +20,8 @@ 6 10800 2400 11272 3999 6 10879 2545 11194 3417 -4 1 0 50 -1 2 17 0.0000 4 205 173 11036 2763 P\001 -4 1 0 50 -1 2 17 0.0000 4 205 205 11036 2981 R\001 -4 1 0 50 -1 2 17 0.0000 4 205 236 11036 3199 O\001 -4 1 0 50 -1 2 17 0.0000 4 205 205 11035 3418 C\001 +4 1 0 50 -1 2 17 0.0000 4 195 180 11036 2763 P\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 11036 2981 R\001 +4 1 0 50 -1 2 17 0.0000 4 195 225 11036 3199 O\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 11035 3418 C\001 -6 2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 @@ -30,7 +30,7 @@ 6 11272 2400 11745 3999 6 11351 2545 11666 3199 -4 1 0 50 -1 2 17 0.0000 4 205 205 11509 2763 R\001 -4 1 0 50 -1 2 17 0.0000 4 205 205 11509 2981 A\001 -4 1 0 50 -1 2 17 0.0000 4 205 268 11509 3199 M\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 11509 2763 R\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 11509 2981 A\001 +4 1 0 50 -1 2 17 0.0000 4 195 270 11509 3199 M\001 -6 2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 @@ -40,15 +40,15 @@ 2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 11824 2473 12139 2473 12139 3926 11824 3926 11824 2473 -4 1 0 50 -1 2 17 0.0000 4 205 110 11981 2763 I\001 -4 1 0 50 -1 2 17 0.0000 4 205 236 11981 2981 O\001 +4 1 0 50 -1 2 17 0.0000 4 195 105 11981 2763 I\001 +4 1 0 50 -1 2 17 0.0000 4 195 225 11981 2981 O\001 -6 6 12217 2400 12690 3999 6 12296 2473 12611 3781 -4 1 0 50 -1 2 17 0.0000 4 205 173 12454 3127 P\001 -4 1 0 50 -1 2 17 0.0000 4 205 205 12454 3345 R\001 -4 1 0 50 -1 2 17 0.0000 4 205 236 12454 3563 O\001 -4 1 0 50 -1 2 17 0.0000 4 205 205 12453 3781 C\001 -4 1 0 50 -1 2 17 0.0000 4 205 236 12454 2909 O\001 -4 1 0 50 -1 2 17 0.0000 4 205 205 12454 2691 C\001 +4 1 0 50 -1 2 17 0.0000 4 195 180 12454 3127 P\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 12454 3345 R\001 +4 1 0 50 -1 2 17 0.0000 4 195 225 12454 3563 O\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 12453 3781 C\001 +4 1 0 50 -1 2 17 0.0000 4 195 225 12454 2909 O\001 +4 1 0 50 -1 2 17 0.0000 4 195 210 12454 2691 C\001 -6 2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 @@ -58,5 +58,5 @@ 2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 10879 4072 12611 4072 12611 4362 10879 4362 10879 4072 -4 1 0 50 -1 2 17 0.0000 4 205 567 11745 4290 BUS\001 +4 1 0 50 -1 2 17 0.0000 4 195 570 11745 4290 BUS\001 -6 -6 @@ -67,23 +67,4 @@ 4 1 0 50 -1 0 12 0.0000 4 195 2085 11790 5040 (bitstream or IP-XACT)\001 4 1 0 50 -1 2 16 0.0000 4 195 495 11820 4815 SoC\001 --6 -6 1665 3300 3315 6107 -6 1665 3300 3315 4275 -2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 - 3240 4200 1740 4200 1740 3375 3240 3375 3240 4200 -4 0 0 50 -1 2 16 0.0000 4 195 585 2265 3750 HPC\001 -4 0 0 50 -1 2 16 0.0000 4 255 1335 1890 4050 application\001 --6 -6 1725 5552 3255 6107 -2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 - 3240 6092 1740 6092 1740 5567 3240 5567 3240 6092 -4 1 0 50 -1 2 16 0.0000 4 195 1095 2490 5927 Function\001 --6 -6 1665 4387 3315 5362 -2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 - 3240 5287 1740 5287 1740 4462 3240 4462 3240 5287 -4 0 0 50 -1 2 16 0.0000 4 195 1245 1965 4837 Embedded\001 -4 0 0 50 -1 2 16 0.0000 4 255 1335 1890 5137 application\001 --6 -6 6 4275 2307 6675 4782 @@ -163,4 +144,16 @@ 4 1 0 50 -1 2 16 0.0000 4 255 1140 8625 3630 Template\001 -6 +6 1650 3268 3300 4243 +2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 + 3225 4168 1725 4168 1725 3343 3225 3343 3225 4168 +4 0 0 50 -1 2 16 0.0000 4 195 585 2250 3718 HPC\001 +4 0 0 50 -1 2 16 0.0000 4 255 1335 1875 4018 application\001 +-6 +6 1650 4355 3300 5330 +2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 + 3225 5255 1725 5255 1725 4430 3225 4430 3225 5255 +4 0 0 50 -1 2 16 0.0000 4 195 1245 1950 4805 Embedded\001 +4 0 0 50 -1 2 16 0.0000 4 255 1335 1875 5105 application\001 +-6 2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 1 1 2.00 60.00 120.00 @@ -182,4 +175,6 @@ 2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 12855 1960 10650 1960 10650 1275 12855 1275 12855 1960 +2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 + 3225 6300 1725 6300 1725 5535 3225 5535 3225 6300 4 0 0 50 -1 2 16 0.0000 4 195 1305 11100 1650 Executable\001 4 0 0 50 -1 2 16 0.0000 4 255 690 2250 675 Input\001 @@ -189,2 +184,4 @@ 4 0 0 50 -1 2 16 0.0000 4 255 2535 4275 6300 Performance analysis\001 4 0 0 50 -1 2 16 0.0000 4 255 2805 10350 6300 Running or Integration\001 +4 1 0 50 -1 2 16 0.0000 4 255 1305 2475 5850 sub-system\001 +4 1 0 50 -1 2 16 0.0000 4 255 1335 2475 6150 application\001 Index: /anr/gantt.l =================================================================== --- /anr/gantt.l (revision 277) +++ /anr/gantt.l (revision 278) @@ -47,10 +47,7 @@ { "ubs" ,"ubs" ,"table_ubs_full.tex" ,"table_ubs_short.tex" }, { "upmc" ,"upmc" ,"table_upmc_full.tex" ,"table_upmc_short.tex" }, - { "altera" ,"altera" ,"table_altera_full.tex" ,"table_altera_short.tex" }, - { "xilinx" ,"xilinx" ,"table_xilinx_full.tex" ,"table_xilinx_short.tex" }, { "bull" ,"bull" ,"table_bull_full.tex" ,"table_bull_short.tex" }, { "thales" ,"thales" ,"table_thales_full.tex" ,"table_thales_short.tex" }, - { "zied" ,"zied" ,"table_zied_full.tex" ,"table_zied_short.tex" }, - { "navtel" ,"navtel" ,"table_navtel_full.tex" ,"table_navtel_short.tex" }, + { "mds" ,"mds" ,"table_mds_full.tex" ,"table_mds_short.tex" }, { 0 ,0 ,0 ,0 }, }; @@ -862,6 +859,6 @@ int main() { - int tnplus[10] = { 1, 2, 3, 4, 8, -1 }; - int tnmoins[10] = { 1, 2, 3, 4, 8, -1 }; + int tnplus[10] = { 1, 2, 3, 4, 5, 6, -1 }; + int tnmoins[10] = { 1, 2, 3, 4, 5, 6, -1 }; yylex(); @@ -876,13 +873,11 @@ prepare3(curr); do_partner_table_full(1); do_partner_table_short(1); - do_partner_table_full(2); do_partner_table_short(3); + do_partner_table_full(2); do_partner_table_short(2); do_partner_table_full(3); do_partner_table_short(3); do_partner_table_full(4); do_partner_table_short(4); do_partner_table_full(5); do_partner_table_short(5); + do_partner_table_full(6); do_partner_table_short(6); do_partner_table_full(7); do_partner_table_short(7); do_partner_table_full(8); do_partner_table_short(8); - do_partner_table_full(9); do_partner_table_short(9); - do_partner_table_full(10); do_partner_table_short(10); - do_partner_table_full(11); do_partner_table_short(10); curr = data_new(0,0); @@ -891,5 +886,5 @@ prepare2(curr); prepare3(curr); - do_livrable_tables(70); + do_livrable_tables(40); return 0; } Index: /anr/section-4.4.tex =================================================================== --- /anr/section-4.4.tex (revision 277) +++ /anr/section-4.4.tex (revision 278) @@ -17,5 +17,5 @@ \hspace*{-.4cm}%\vspace{-1.5cm} \input{gantt1.tex} -\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4 and task-8)} +\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)} \end{figure} @@ -23,5 +23,5 @@ \hspace*{-.4cm}%\vspace{-1.5cm} \input{gantt2.tex} -\caption{\label{gantt2}Gantt diagram of deliverables (task-5, task-6 and task-7)} +\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)} \end{figure} @@ -74,6 +74,5 @@ % Our experience with UGH and GAUT give us confidence in the succes of this % task. -\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC}, - {\csgXilinxSystemC})] +\item[Virtual prototyping of \altera \& \xilinx architectural templates (\novers{\csgImplementation})] The SoCLib component library contains several SystemC models used for the virtual prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores). Index: /anr/section-7.tex =================================================================== --- /anr/section-7.tex (revision 277) +++ /anr/section-7.tex (revision 278) @@ -169,6 +169,7 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 6: \xilinx} - +\subsection{Partner 6: \mds} + +\begin{ADDEDENV} \begin{description} \item[Equipment] @@ -178,5 +179,5 @@ The man power detail in \hommemois by deliverables is given in figure~\ref{table-livrables-1} and a sumary by task in the following table. - \begin{center}\input{table_xilinx_short.tex}\end{center} + \begin{center}\input{table_mds_short.tex}\end{center} \item[Subcontracting] No subcontracting costs. @@ -187,4 +188,5 @@ \item[Other working costs] none \end{description} +\end{ADDEDENV} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -234,48 +236,4 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 9: \zied} - -\begin{description} -\item[Equipment] - No equipement costs. -\item[Personnel costs] - The effort to define SoC architecture and adapt eFPGA interface to generate is - estimated to 9.6 \hommemois. - The effort to develop demonstrator and to extract eFPGA timining characteristics is - estimated to 4.8 \hommemois. - Finally we need one 3.6 man.month for the evaluation of the FLEXRAS solution. - The table below summarizes the these manpower costs in \hommemois for the deliverables - and by tasks. - \begin{center}\input{table_zied_full.tex}\end{center} -\item[Subcontracting] - No subcontracting costs. -\item[Travel] - No travel costs. -\item[Expenses for inward billing] none -\item[Other working costs] none -\end{description} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 10: \navtel} - -\begin{description} -\item[Equipment] - Navtel will use FPGA board with ARM processors for the validation. - The costs for depreciation of the board and the instrument of test - are evaluated to 7\% of the total requested ANR funding. -\item[Personnel costs] - A permanent engineer will be assigned on average 1/3 time for - all the duration of the project. - The table below shows the estimated manpower cost in \hommemois for the deliverables - and by tasks. - \begin{center}\input{table_navtel_full.tex}\end{center} -\item[Subcontracting] - No subcontracting costs. -\item[Travel] - The travel costs are associated to meeting, plenaries as well as participation to - conferences. The travel costs are estimated to 3 k\euro. -\item[Expenses for inward billing] none -\item[Other working costs] none -\end{description} % \begin{landscape} @@ -286,5 +244,5 @@ \begin{minipage}[b]{.47\linewidth}\center \input{table_inria_cairn_full.tex}\vspace{.5ex}\\ \irisa \vspace{2.5ex}\\ -\input{table_xilinx_full.tex}\vspace{.5ex}\\ \xilinx\\ +\input{table_mds_full.tex}\vspace{.5ex}\\ \mds \\ \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center \input{table_tima_full.tex}\vspace{.5ex} \\ \tima Index: /anr/task-0.tex =================================================================== --- /anr/task-0.tex (revision 277) +++ /anr/task-0.tex (revision 278) @@ -1,4 +1,4 @@ \begin{taskinfo} -\let\UPMC\leader +\let\MDS\leader \let\ALL\enable \end{taskinfo} @@ -20,19 +20,19 @@ % \begin{workpackage} - \subtask This \ST consists in writing and ratifying the consortium agreement. + \subtask{Consortium agreement} This \ST consists in writing and ratifying the consortium agreement. \begin{livrable} \CoutHorsD{0}{36}{\Subs}{project management}{1:1:1} - \itemL{0}{6}{d}{\Supmc}{Consortium agreement}{1:0:0} + \itemL{0}{6}{d}{\Smds}{Consortium agreement}{1:0:0} A document describing the consortium agreement, signed by all the partners. \end{livrable} - \subtask This \ST concerns the global management of the deliverables and of the global + \subtask{Global management} This \ST concerns the global management of the deliverables and of the global organization of the project at all the levels. \begin{livrable} - \itemL{0}{36}{d}{\Supmc}{Global management}{1:1:1} + \itemL{0}{36}{d}{\Smds}{Global management}{1:1:1} Global management of the project at all the levels: progress monitoring, record keeping, meeting organization, review organization, the writing of the review reports. \end{livrable} - \subtask This \ST consists in managing the project at the partner level. + \subtask{Partner level management} This \ST consists in managing the project at the partner level. It includes mainly the progress monitoring, the record keeping the participation to the project meetings and the communication with the project leader and the other partners. @@ -41,6 +41,7 @@ \CoutHorsD{0}{36}{\Stima}{project management}{1:1:1} \end{livrable} - \subtask This \ST consists firstly in the building, and next in the administration and the - maintenance of the development and dissemination infrastructure. It is also in charge of + \subtask{Setup of dissemination infrastructure} + This \ST consists firstly in the building, and next in the administration and the + maintenance of the development and dissemination infrastructure. It is also in charge of the COACH releases distribution. \begin{livrable} Index: /anr/task-1.tex =================================================================== --- /anr/task-1.tex (revision 277) +++ /anr/task-1.tex (revision 278) @@ -12,7 +12,8 @@ % \begin{workpackage} -\subtask This \ST specifies the COACH environment for the system designer. At this - level the COACH framework is a black box. The deliverables are documents - specifying: how to feed COACH (the inputs), how to use COACH (the design flow), +\subtask{Specification of the COACH environment} + This \ST specifies the COACH environment for the system designer. In this + \ST the COACH framework is a black box. The deliverables are documents + specifying: how to feed COACH (the inputs), how to use COACH (use model), what is generated (the outputs). %(definition of the generic architecture of the @@ -22,5 +23,5 @@ \itemV{0}{6}{d}{\Supmc}{COACH specification} \setMacroInAuxFile{specGenManualI} The first version of the COACH specification. - This document contains the general description of the framework, the design flow and the + This document contains the general description of the framework, the use model and the description of the architectural templates. It refers to the HAS specification (deliverable {\specHasManual}) and @@ -50,5 +51,6 @@ feed-backs of the demonstrator \STs. \end{livrable} -\subtask This \ST specifies the software COACH structure. The deliverable is a +\subtask{Internal software structure} + This \ST specifies the COACH software structure. The deliverable is a document listing all the COACH software components and how they cooperate. \begin{livrable} @@ -57,5 +59,6 @@ Description of the software list and the data flow among the tools. \end{livrable} -\subtask This \ST specifies the \xcoach and the \xcoachplus formats. +\subtask{\xcoach format} + This \ST specifies the \xcoach and the \xcoachplus formats. \begin{livrable} \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification} @@ -74,21 +77,25 @@ \itemV{6}{12}{x}{\Subs}{First release of C2X} \setMacroInAuxFile{specXcoachToCAI} - A GCC plugin C2X that generates a \xcoach description + This delivrable groups 2 tools. + The first one C2X is a GCC plugin that generates a \xcoach description (defined in {\specXcoachDocI} deliverable) from a C/C++ task description (defined in {\specHasManual} deliverable). - \itemL{12}{18}{x}{\Subs}{C2X tool}{2:1:0} + The second one X2C regenerates a C description from a \xcoach + description. + % TACHE INCLUSE mais non decrite; Specification of the GCC driver tool. + \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0} \setMacroInAuxFile{specXcoachToCA} - An updated version of C2X (\specXcoachToCAI) which supports the \xcoach format defined + An updated version of C2X and X2C (\specXcoachToCAI) which supports the \xcoach format defined in the {\specXcoachDoc} deliverable and the HAS input format defined in the {\specHasManual} deliverable. - \itemV{7}{12}{x}{\Subs}{First release of X2C} - \setMacroInAuxFile{specXcoachToCBI} - This second tool X2C regenerates a C description from a \xcoach - description. - \itemL{12}{18}{x}{\Subs}{X2C tool}{2:1:0} - \setMacroInAuxFile{specXcoachToCB} - The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined - in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual} - deliverable. +% \itemV{7}{12}{x}{\Subs}{First release of X2C} +% \setMacroInAuxFile{specXcoachToCBI} +% This second tool X2C regenerates a C description from a \xcoach +% description. +% \itemL{12}{18}{x}{\Subs}{X2C tool}{2:1:0} +% \setMacroInAuxFile{specXcoachToCB} +% The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined +% in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual} +% deliverable. \itemV{12}{18}{x}{\Supmc}{First release of X2SC} \setMacroInAuxFile{specXcoachToSystemCI} @@ -106,25 +113,20 @@ Final release of the former software (\specXcoachToVhdlI) and integration of enhancements proposed in \novers{\specXilinxOptimization} deliverable. - \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0} - \setMacroInAuxFile{specXilinxOptimization} - This deliverable consists in optimizing the VHDL generated from \xcoachplus format - (deliverable \novers{\specXcoachToVhdl}) for the \xilinx RTL synthesis tools. - \ubs will provide several examples of VHDL source files generated from \xcoachplus, - with explanations about generation process of main data structures used in VHDL sources, - \xilinx will provide back a documentation listing that proposes VHDL generation enhancements. \end{livrable} -\subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler. - \begin{livrable} - \itemL{0}{3}{d}{\Subs}{GCC driver specification}{1:0:0} - Specification of the GCC driver tool. - \itemV{3}{9}{x}{\Subs}{GCC driver} - First release of the GCC driver tool. - %en T0+18 car va peut etre evoluer en fonction du DSE µ-archi - \itemL{9}{12}{x}{\Subs}{GCC driver}{3:0:0} - Final release of the GCC driver tool. - \end{livrable} +% TACHE INCLUSE SANS X2C & C2X +%\subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler. +% \begin{livrable} +% \itemL{0}{3}{d}{\Subs}{GCC driver specification}{1:0:0} +% Specification of the GCC driver tool. +% \itemV{3}{9}{x}{\Subs}{GCC driver} +% First release of the GCC driver tool. +% %en T0+18 car va peut etre evoluer en fonction du DSE µ-archi +% \itemL{9}{12}{x}{\Subs}{GCC driver}{3:0:0} +% Final release of the GCC driver tool. +% \end{livrable} -\subtask Backend HLS tools use a characterized macro-cell library to build the +\subtask{Tool for cell library creation} + Backend HLS tools use a characterized macro-cell library to build the micro-architecture of a coprocessor. The characterisation of a cell depends on the target device. The role of this \ST is to define the macro-cells and Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 277) +++ /anr/task-2.tex (revision 278) @@ -12,110 +12,46 @@ Its objective is to allow the system designer to explore the design space by quickly prototyping and then to automatically generate the FPGA-SoC systems. -This task consists of +This task consists of: \begin{itemize} -\item The development of all the missing components (SytemC models and/or synthesizable VHDL models -of the IP-cores), +\item The development of the synthesizable models required for the connection of +the coprocessors on the platform bus (2 bridges). \item The configuration and the development of drivers of the operating systems (Board Support Package, HAL), \item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system including its bitstream and software executable code, -\item The specification of enhanced communication schemes and their sofware and hardware implementations. \end{itemize} -This task being based on the SoCLib platform, a first release will be delivered at $T0+12$ -to allow the demonstrators to start working. -This release will include the standard communication schemes (based on SoCLib MWMR component) +A first release will be delivered at $T0+12$ to allow the demonstrators to start working. +This release will include the standard communication schemes based on SoCLib MWMR component and support the neutral architectural template for prototyping and hardware generation. \end{objectif} % \begin{workpackage} -\subtask This \ST corresponds to the COACH System Generator (CSG) software. +\subtask{Bridge implementation} + This \ST deals with the development of the synthesizable models required for the connection of + the coprocessors on the platform bus). \begin{livrable} - \itemV{0}{12}{x}{\Supmc}{CSG tool} \setMacroInAuxFile{csgCoachArch} - The first software release of the CSG tool that will allow demonstrators to start - working by using the neutral architectural template. - \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} - The second release of CSG supports the \xilinx and \altera architectural - templates and the enhanced communication system, but only for SystemC prototyping. - This release integrates a first integration of HLS tools. - \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} - This milestone extends CSG (\csgPrototypingOnly) to - FPGA-SoC generation for the \xilinx and \altera architectural template. - \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} - Final release of CSG. + \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} + \setMacroInAuxFile{hpcPlbBridge} + The synthesizable VHDL description of a PLB/VCI bridge. + \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} + \setMacroInAuxFile{hpcAvalonBridge} + The synthesizable VHDL description of an AVALON/VCI bridge. \end{livrable} -\subtask This \ST deals with the components of the architectural templates. - \\ - For the neutral architectural template, it consists of the development of the VHDL - synthesizable description of the missing communication components (MWMR) - in order to support the process network communication model. - Notice that the SystemC models - comes from the SocLib ANR project, the processor with its cache comes from the TSAR - ANR project. - \\ - For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...). - \begin{livrable} - \itemL{0}{12}{h}{\Supmc}{Neutral architecture}{1:0:0} - \setMacroInAuxFile{csgCoachArchTempl} - The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. - \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0} - This deliverable consists in optimizing the VHDL descriptions of the components of - the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the - \xilinx RTL synthesis tools. - \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation - listing that proposes VHDL generation enhancements. - \itemV{6}{18}{x}{\Stima}{\xilinx architecture} - \setMacroInAuxFile{csgXilinxSystemC} - The SystemC simulation module of the MWMR component with a PLB bus interface plus - the SystemC modules of the components of the \xilinx architectural template - currently not available in the SocLib component library. - \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0} - The synthesizable VHDL description of the MWMR component corresponding to the - SystemC module of the former deliverable (\csgXilinxSystemC). - \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5} - This deliverable consists in optimizing the MWMR VHDL description (deliverable - \novers{\csgXilinxSystemC}) of the \xilinx architectural template. - \tima will provide MWMR VHDL description, \xilinx will provide back a documentation - listing that proposes VHDL generation enhancements. - \itemV{6}{18}{x}{\Sirisa}{\altera architecture} - \setMacroInAuxFile{csgAlteraSystemC} - The SystemC simulation module of the MWMR component with an AVALON bus interface plus - the SystemC modules of the components of the \altera architectural template - currently not available in the SocLib component library. - \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0} - The synthesizable VHDL description of the MWMR component corresponding to the - SystemC module of the former deliverable (\csgAlteraSystemC); - \itemL{6}{12}{d}{\Subs}{Communication adapter spec.}{1:0:0} - \setMacroInAuxFile{gautCOMMoptimization} - Specification of an optimized communication adapter (space and time) component to handle data interleaving. - This evolution aims to solve out of order communication weakness of the classical MWMR. - \itemV{12}{24}{x}{\Subs}{Communication adapter}{0:6:0} - First release of the tool that generates the VHDL description of the optimized communication adapter - and its corresponding SystemC module. - \itemL{24}{30}{x}{\Subs}{Comm. adapter generator}{0:6:3} - Final release of the tool that generates the VHDL description of the optimized - communication adapter and its corresponding SystemC module (\gautCOMMoptimization). - \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5} - This deliverable consists in optimizing the communication adapter VHDL description (deliverable - \novers{\gautCOMMoptimization}). - \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation - listing that proposes VHDL generation enhancements. - \end{livrable} -\subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating - system and the development of drivers for the hardware architectural templates - and enhanced communication schemes defined in \novers{\specCsgManual} deliverable. +\subtask{OS setup} This \ST consists of the configuration of the SocLib DNA operating + system and the development of drivers for the hardware architectural templates. For the \altera and \xilinx architectural templates, the OSs must also be ported on the NIOS2 and MICROBLAZE processors. \begin{livrable} - \itemV{6}{8}{x}{\Supmc}{MUTEKH OS} - The drivers required for the first CSG milestone (deliverable \csgCoachArch). - \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers} - The drivers required for the second CSG milestone ({\csgPrototypingOnly}). - \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2} - Final release of the MUTEKH OS drivers. - \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0} - Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors. +%IVG \itemV{6}{8}{x}{\Supmc}{MUTEKH OS} +%IVG The drivers required for the first CSG milestone (deliverable \csgCoachArch). +%IVG \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers} +%IVG The drivers required for the second CSG milestone ({\csgPrototypingOnly}). +%IVG \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2} +%IVG Final release of the MUTEKH OS drivers. +%IVG \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0} +%IVG Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors. \itemV{6}{8}{x}{\Stima}{DNA OS} - The drivers required for the first CSG milestone (deliverable \csgCoachArch). + The drivers required for the first CSG milestone. \itemV{8}{18}{x}{\Stima}{DNA 0S} - The drivers required for the second CSG milestone ({\csgPrototypingOnly}). + The drivers required for the second CSG milestone. \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2} Final release of the DNA OS drivers. @@ -123,3 +59,18 @@ Porting of DNA OS on the NIOS2 and MICROBLAZE processors. \end{livrable} +% +\subtask{Implementation of CSG} This \ST corresponds to the COACH System Generator (CSG) software. + \begin{livrable} + \itemV{0}{12}{x}{\Supmc}{CSG tool} + The first software release of the CSG tool that will allow demonstrators to start + working by using the neutral architectural template only for SystemC. + \itemV{12}{18}{x}{\Supmc}{CSG} + The second release of CSG integrates the VHDL driver for the neutral + architectural template, and an integration of an HLS tools + but only for SystemC prototyping. + \itemV{18}{24}{x}{\Supmc}{CSG} + This release extends CSG to FPGA-SoC generation for the \xilinx and \altera architectural template. + \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} \setMacroInAuxFile{csgImplementation} + Final release of CSG enhanced by the demonstrator's feedback. + \end{livrable} \end{workpackage} Index: /anr/task-3.tex =================================================================== --- /anr/task-3.tex (revision 277) +++ /anr/task-3.tex (revision 278) @@ -21,5 +21,6 @@ % \begin{workpackage} - \subtask This sub-task aims at providing compiler support for custom instructions + \subtask{ASIP compiler} + This sub-task aims at providing compiler support for custom instructions within the HAS front-end. It will take as input the COACH intermediate representation, and will output an annotated COACH IR containing the custom @@ -36,5 +37,6 @@ \end{livrable} - \subtask In this sub-task, we provide micro-architectural template models for the two target + \subtask{Micro-architectural template models for ASIP} + In this sub-task, we provide micro-architectural template models for the two target processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) @@ -46,7 +48,4 @@ {A SystemC simulation model for an extensible MIPS with a tight architectural integration of its instruction set extensions} - \itemL{0}{12}{x}{\Sirisa}{SystemC for NIOS processor}{2:0:0} - { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being - already available from \altera} \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS} {A synthesizable VHDL model for a simple extensible MIPS architectural template} @@ -59,6 +58,6 @@ \end{livrable} - \subtask Extraction of parallelism in polyhedral loops and conversion into a process network. - + \subtask{Parallelism optimization} + Extraction of parallelism in polyhedral loops and conversion into a process network. \begin{livrable} \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition} Index: /anr/task-4.tex =================================================================== --- /anr/task-4.tex (revision 277) +++ /anr/task-4.tex (revision 278) @@ -9,6 +9,5 @@ The objectives of this task are to provide the two HAS back-ends of the COACH project and a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required -by the processors and the system BUS. -%pourquoi en majuscule? +by the processors and the system bus. \\ The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an @@ -22,57 +21,29 @@ UGH. These tools are complementary and not in competition because they cover respectively data and control dominated designs. -The organization of the task is firstly to quickly integrate the existing HLS to the COACH -framework. Secondly these tools will be improved to allows to treat data dominated application -with a few control for GAUT and control dominated application with a few data processing -for UGH. This will enlarge the domain the HLS can cover which is a strong limitation of the -tools currently avilable \cite{HLSBOOK} \cite{IEEEDT} \cite{CATRENE}. \end{objectif} -%FIXMA == {il faudrait fusionner les taches ST5-1 et ST5-2, non ???} \begin{workpackage} -\subtask The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It - consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing - them by \xcoach and \xcoachplus drivers i.e. C2X, X2SC and X2VHDL. +\subtask{Making HAS back-end to read \xcoach format} + The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. + by implementing the mechanism to read \xcoach format. \begin{livrable} \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0} Release of the UGH software that reads \xcoach format. - \itemV{12}{18}{x}{\Supmc}{UGH integration} - Release of the UGH software that writes \xcoachplus format. - \itemL{18}{33}{x}{\Supmc}{UGH integration}{0:2:4.0} - Final release of the UGH software. - \end{livrable} -\subtask The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It - consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing - them by \xcoach and \xcoachplus drivers. - \begin{livrable} \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0} Release of the GAUT software that is able to read \xcoach format. + \end{livrable} +% +\subtask{Making HAS back-end to write \xcoachplus format} + The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. + by implementing the mechanism to write \xcoachplus format. + \begin{livrable} + \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0} + Release of the UGH software that writes \xcoachplus format. \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0} Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format. - %\itemL{18}{33}{x}{\Subs}{Final release of GAUT}{0:1:6} - % Final release of the GAUT software. \end{livrable} -\subtask The goal of this \ST is to improve the UGH and GAUT HLS tools. - UGH and GAUT experimentations have shown respectively usefull enhancements. - \begin{livrable} - \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:9:0} - Release of the UGH software with support for treating automatically data dominated sections - included into a control dominated application. - \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:3:6} - Release of the UGH software able to generate a micro-architecture without the - variable binding currently done by the designer. - \itemL{12}{24}{x}{\Subs}{Release of GAUT with \ganttlf enhanced synthesis steps}{0:9:0} - Release of the GAUT software that supports the \xcoach model during the binding and the scheduling steps. - \itemL{24}{33}{x}{\Subs}{Release of GAUT supporting \ganttlf new const./obj.}{0:0:7} - Release of the GAUT software that supports the \xcoach model during the binding and the scheduling steps - and also supports new constraints and objectives. - \itemV{18}{24}{d}{\Subs}{Micro-architecture Exploration}\setMacroInAuxFile{MAE} - Specification of a Design Space Exploration framework for the HAS Back-end: - The high level specification tools, such as GAUT, have to be able to use synthesis feed-back - informations in order to explore the design space and to generate optimized architectures. - \itemL{24}{36}{x}{\Subs}{Micro-architecture Exploration}{0:4:4} - Release of the GAUT software that supports the features defined in \MAE - \end{livrable} -\subtask In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors + +\subtask{Coprocessor frequency adaptation} + In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors generated by HLS synthesis must respect this frequency. However, the HLS tools can not guarantee that the micro-architectures they generate accurately respect this @@ -84,5 +55,5 @@ \begin{livrable} \itemV{0}{12}{d}{\Supmc}{Frequency calibration} - A document describing the set up of the coprocessor frequency calibration.: + A document describing the set up of the coprocessor frequency calibration. \itemV{12}{24}{x}{\Supmc}{Frequency calibration} \setMacroInAuxFile{freqCalibrationVhdl} @@ -91,9 +62,4 @@ The frequency calibration software consists of a driver in the FPGA-SoC operating system and of a control software. - \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (5)}{0:0:1.5} - This deliverable consists in optimizing the VHDL description provided in - \novers{\freqCalibrationVhdl}. - \upmc will provide the VHDL description, \xilinx will provide back a documentation - listing that proposes VHDL generation enhancements. \end{livrable} \end{workpackage} Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 277) +++ /anr/task-5.tex (revision 278) @@ -20,6 +20,6 @@ \item Implementing the communication scheme at all levels: partition help, software implementation both on the PC and in the operating system of the FPGA-SoC, hardware. -\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order -to optimize FPGA ressource usage. +%\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order +%to optimize FPGA ressource usage. \end{itemize} @@ -33,7 +33,7 @@ % \begin{workpackage} - \subtask + \subtask{Implementation of API between PC and FPGA-SoC} This \ST deals with the COACH HPC feature that consists in accelerating an existing - apllication running on a PC by migrating critical parts into a SoC implemented on an + application running on a PC by migrating critical parts into a SoC implemented on an FPGA plugged to the PC PCI/X bus. The main steps and components of this \ST are: @@ -54,31 +54,33 @@ \setMacroInAuxFile{hpcCommHelper} A library implementing the communication API defined in the {\hpcCommApi} deliverable. - This library is dedicated to help the end-user to partition an applicattion for - HPC. + This library is dedicated to help the end-user to partition an application for HPC. \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0} \setMacroInAuxFile{hpcCommLinux} - The PC part of the HPC communication API that comminicates with the FPGA-SOC, a - library and probably a LINUX module. - \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0} - \setMacroInAuxFile{hpcMutekDriver} - The FPGA-SoC part of the communication API, a driver. + The PC part of the HPC communication API that communicates with the FPGA-SOC, a + library and a LINUX module. +% \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0} +% \setMacroInAuxFile{hpcMutekDriver} +% The FPGA-SoC part of the communication API, a driver. \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} \setMacroInAuxFile{hpcDnaDriver} - Port of the {\hpcMutekDriver} driver on the DNA OS. - \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} - Bug corrections and enhancements of communication middleware - (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux}, - \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}). + The FPGA-SoC part of the communication API. +% Port of the {\hpcMutekDriver} driver on the DNA OS. +% \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} +% Bug corrections and enhancements of communication middleware +% (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux}, +% \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}). \end{livrable} -\subtask This \ST deals with the implementation of hardware and SystemC modules +\subtask{SystemC model of the PCI/X} + This \ST deals with the implementation of hardware and SystemC modules required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. \begin{livrable} - \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} - \setMacroInAuxFile{hpcPlbBridge} - The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. - \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} - \setMacroInAuxFile{hpcAvalonBridge} - The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. +% FIXME: moved to task 3 (CSG) +% \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} +% \setMacroInAuxFile{hpcPlbBridge} +% The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. +% \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} +% \setMacroInAuxFile{hpcAvalonBridge} +% The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} The SystemC description of a component that generates PCI/X traffic. It is @@ -86,34 +88,34 @@ \end{livrable} -\subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. -It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. - \begin{livrable} - \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} - Modification of the CSG software to support statically reconfigurable tasks. - \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} - This livrable is a CSG module allowing to partition the task graph along - the dynamic partial reconfiguration regions. The resulting task-region assignement - is directly used for generation of bitstreams. The module also produces reconfiguration - management software to be run on the SoC-FPGA. - \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3} - \setMacroInAuxFile{hpcDynconfDriver} - The drivers required by the DNA OS in order to manage dynamic partial - reconfiguration inside the SoC-FPGA. - \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for MUTEKH drivers}{0:0:1} - Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. - \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} - Extension of the HPC partionning helper in order to integrate dynamic partial - reconfiguration dedicated features (reconfiguration time of regions, variable - number of coprocessors). - \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2} - \xilinx will work with \tima in order to better take into account during - partitioning decisions specific constraints due to partial reconfiguration process. - The deliverable is a document describing the \xilinx specific constraints. - \end{livrable} -%\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board -% with its PCI/X IP. These boards are dedicated to the COACH HPC development. -% They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. -% \begin{livrable} -% \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. -% \end{livrable} +% \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. +% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. +% \begin{livrable} +% \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} +% Modification of the CSG software to support statically reconfigurable tasks. +% \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} +% This livrable is a CSG module allowing to partition the task graph along +% the dynamic partial reconfiguration regions. The resulting task-region assignement +% is directly used for generation of bitstreams. The module also produces reconfiguration +% management software to be run on the SoC-FPGA. +% \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3} +% \setMacroInAuxFile{hpcDynconfDriver} +% The drivers required by the DNA OS in order to manage dynamic partial +% reconfiguration inside the SoC-FPGA. +% \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for MUTEKH drivers}{0:0:1} +% Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. +% \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} +% Extension of the HPC partionning helper in order to integrate dynamic partial +% reconfiguration dedicated features (reconfiguration time of regions, variable +% number of coprocessors). +% \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2} +% \xilinx will work with \tima in order to better take into account during +% partitioning decisions specific constraints due to partial reconfiguration process. +% The deliverable is a document describing the \xilinx specific constraints. +% \end{livrable} +% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board +% % with its PCI/X IP. These boards are dedicated to the COACH HPC development. +% % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. +% % \begin{livrable} +% % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. +% % \end{livrable} \end{workpackage} Index: /anr/task-6.tex =================================================================== --- /anr/task-6.tex (revision 277) +++ /anr/task-6.tex (revision 278) @@ -13,5 +13,5 @@ % \begin{workpackage} - \subtask + \subtask{\bull HPC demonstrator} The application that \bull proposes is HPC oriented. The domain of the application is the treatment of medical images (image noise @@ -31,6 +31,6 @@ \end{livrable} - \subtask - The objective of this sub-task is to specify the THALES application and to develop the + \subtask{\TRT Embedded SoC demonstrator} + The objective of this sub-task is to specify the \TRT application and to develop the high level code. This application is in the domain of surveillance of critical infrastructures. The objective is to detect and classify the presence of humans in the @@ -53,9 +53,10 @@ This deliverable is a document that specifies the application. \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0} - This deliverable is the code of the application spcecified former + This deliverable is the code of the application specified former deliverable (\trtAppSpecification). \end{livrable} - \subtask \TRT will use its internal software environment tool SPEAR DE to describe the + \subtask{SPEAR-DE adaptation for COACH} + \TRT will use its internal software environment tool SPEAR DE to describe the application. The tool is able to partition and to generate the code for the target. \\ In this task, we will adapt SPEAR DE to generate the application description input of @@ -68,5 +69,14 @@ \end{livrable} - \subtask + \subtask{\mds use case} + \mds will use ................. + \begin{livrable} + \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0} + \setMacroInAuxFile{trtSpearde} + Adaptation of SPEAR-DE for COACH framework. + \end{livrable} + + \subtask{Evaluation report} + % FIXME: AJOUTER une evaluation de BULL ET MDS In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify its ability to generate a whole VHDL of an embedded system on FPGA for an application @@ -88,92 +98,3 @@ \end{livrable} - \subtask FLEXRAS will design an application based on M-JPEG video standard. - FLEXRAS will propose a SoC architecture integrating an embedded FPGA (eFPGA). - The architecture is composed essentially of a processor, a bus and several RAMs. - The embedded FPGA is connected to the bus and communicates with the other components. - The (eFPGA) works in 2 modes: - \begin{description} - \item[Slave mode] - As a DMA, the processor will send the configuration bitstream - stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a - writeable memory and is configured by the processor. - \item[Master mode] - Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task. - \end{description} - The top architecture of this SoC based-platform will be generated using COACH - framework. The application that will be run on the SoC corresponds initially to a - graph of software tasks. Critical tasks will be identified and transformed - automatically to hardware tasks using COACH high level synthesis feature. While - software tasks will be run on the processor, hardware ones will be mapped on eFPGA - to take advantage of its optimized resources and parallelism. FLEXRAS provides all - the flow from RTL synthesis to bitstream generation. - \begin{livrable} - \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0} - FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to - generate the SoC architecture. - This deliverable is a document that describes this architecture. - \itemL{6}{18}{h}{\Szied}{eFPGA/VCI component}{3.6:3.6:0} - FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus. - This deliverable is a VHDL description. -% \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0} -% Port of the bitstream loader to the MUTEKH operating system. - \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0} - \zied will propose to test COACH framework and the \zied architecture template - throught an application based on M-JPEG video standard. - This applicattion will containt 3 communicating tasks under the COACH format specified - in {\novers{\specGenManual}} deliverable. - The first one is a hardware task generated by the HAS tools and transformed into - a bit stream by the \zied tools. - The second is a bitstream loader that will load the bitstream of the first task on - the eFPGA. - The third is a software task that communicates with the hw task for testing it. - \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4} - This deliverable is a file under the format defined by the deliverable - {\specMacroCell} that characterizes the eFPGA. This will allow the COACH HLS tools - to take into account the eFPGA delays. - \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6} - This deliverable is a document that describes the tests, the validation and the - evaluation of COACH with the \zied architecture and tools. - \end{livrable} - - \subtask - The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly - coupled module between %ARM - a embedded processor and an FPGA both on a board. - By using the COACH environment, \navtel will automatically synthetize two cores: one for software radio - through a polyphase resampler and one for an industrial control application through an embedded - PID controller. - The objective is to sequence the cores in realtime in FPGA using partial configuration methods - proposed in the COACH project. - This will allow us to gain experience on automatic multi core sequencing at system level. The - specification for our first work package will concern this aspect. - - The ESC can function on different topologies: Single, parallel or Grid computing modes for - industrial and scientific applications. - %The ARM - The processor and FPGA configuration also facilitate the co-simulation which allows to gain - time on the development and integration phase. - The architecture consists of a wrapper that encapsules computing units depending on the - application and a real time kernal for task switching and partial reconfiguration of FPGA - on run time environment. - \parlf - To day \navtel develops these computing units manually. - \navtel expects to benefit from the COACH project especially the HLS tools for - generating the computing unit. - \begin{livrable} - \itemL{0}{6}{d}{\Snavtel}{\navtel \ganttlf demonstrator specification}{4:0:0} - \setMacroInAuxFile{navtelSpecification} - A document that will define the requirements for automatic RTL generation for - signal processing units of our market sector such as digital communication, - imaging and industrial control. - This document will include the description of some already handmade processing units. - \itemL{6}{18}{h}{\Snavtel}{\navtel \ganttlf wrapper adaptation}{1:1:0} - The adaptation of our wrapper to support coprocessor generated by COACH. - \itemL{18}{36}{d}{\Snavtel}{\navtel evaluation}{0:2:4} - \navtel will test the COACH HLS tools on the processing units that are described - in the {\navtelSpecification} deliverable. - A document will be written that describes the results obtained taking into - account: 1) the performance in terms of space, 2) the performance in terms of - time, 3) the friendlyness of the environment. - \end{livrable} \end{workpackage} Index: /anr/task-7.tex =================================================================== --- /anr/task-7.tex (revision 277) +++ /anr/task-7.tex (revision 278) @@ -1,4 +1,4 @@ \begin{taskinfo} -\let\UPMC\leader +\let\MDS\leader \let\ALL\enable \end{taskinfo} @@ -20,5 +20,5 @@ % \begin{workpackage} - \subtask This \ST relates to the management of the WEB site and to the distribution of + \subtask{\mustbecompleted{TITLE}} This \ST relates to the management of the WEB site and to the distribution of the COACH releases. \begin{livrable} @@ -38,5 +38,5 @@ \CoutHorsD{12}{36}{\Stima}{dissemination}{0:2:1} \end{livrable} - \subtask + \subtask{\mustbecompleted{TITLE}} \label{subtask-tutorial} This \ST consists of making a COACH tutorial and to publish it on the public WEB @@ -59,9 +59,6 @@ \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1} The final release of the tutorial. - \itemL{30}{33}{d}{\Sxilinx}{\xilinx feedback}{0:0:0.5} - \xilinx will check that the developped tutorial works well with \xilinx tools, - and will propose corrections or enhancements if needed into a document. \end{livrable} - \subtask + \subtask{\mustbecompleted{TITLE}} This \ST consists of making the COACH user reference manuals. They will be published on the public WEB site.