Changeset 281 for anr


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Timestamp:
Nov 30, 2010, 6:12:44 PM (14 years ago)
Author:
coach
Message:

Cleanup and first release for 2011.

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1 edited

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  • anr/section-1.tex

    r269 r281  
    1212Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
    1313implement a complete MPSoC with multiple processors and several dedicated
    14 coprocessors for a few Keuros per device. Many applications are initially captured
     14coprocessors for a few Keuros per device.
     15\\
     16Many applications are initially captured
    1517algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
    1618in tools that can provide an implementation path directly from HLLs to hardware.
     
    2325designs written in C/C++ language and implementing the function straight into FPGA.
    2426We believe that coupling FPGA technologies and ESL methodologies
    25 will allow both SMEs (Small and Medium Enterprise) and
    26 major companies to design innovative devices and to enter new, low and
    27 medium volume markets.
    28 \parlf
     27will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
     28devices and to enter new, low and medium volume markets.
     29\begin{ADDEDENV}
     30Furthermore, today there is an increasing industrial interest to IC
     31that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
     32such as ATOM E600C (Intel).
     33Probably in few years, one can expect that such chips will become current and even standard
     34general purpose CPU cores will contains a configurable area making explode the low and medium volume
     35markets of digital systems.
     36\end{ADDEDENV}
     37\parlf
     38\begin{SUPPRESSEDENV}
    2939The objective of COACH is to provide an integrated design flow, based on the
    3040SoCLib infrastructure~\cite{soclib}, and optimized for the design of
    3141multi-processors digital systems targeting FPGA devices.
    32 Such digital systems are generally integrated
    33 into one or several chips, and there are two types of applications:
     42The digital systems are generally integrated into one or several chips, and there are two types of applications:
    3443They can be embedded (autonomous) applications
    35 such as personal digital assistants (PDA), ambiant computing components,
     44such as personal digital assistants (PDA), ambient computing components,
    3645or wireless sensor networks (WSN).
    3746They can also be extension boards connected to a PC to accelerate a specific computation,
    3847as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
     48\end{SUPPRESSEDENV}\begin{ADDEDENV}
     49The objective of COACH is to provide an integrated design flow for the design of
     50multi-processors digital systems targeting FPGA devices.
     51It will be dedicated to system/software designers, and hide as much as possible
     52the hardware characteristics to the end-user.
     53COACH will mainly target three kinds of digital systems:
     541) embedded and autonomous application such as  personal digital assistants (PDA),
     55   ambient computing components, or wireless sensor networks (WSN);
     562) PCI/E extension boards connected to a PC to accelerate a specific application,
     57   it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
     583) sub-system application for generating an IP to a larger system.
     59\end{ADDEDENV}
    3960\parlf
    4061%verrous scientifiques et techniques
     
    4263\begin{description}
    4364\item[Design Space Exploration:]
    44 
    4565    The COACH environment will allow to describe an application as a process
    4666        network i.e. a set of tasks communicating through FIFO channels.
     
    5070    For each point in the design space, metrics such as throughput, latency, power
    5171    consumption, silicon area, memory allocation and data locality will be provided.
     72    \begin{SUPPRESSEDENV}
    5273    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
    5374    and high-level estimation methodologies.
    54        
     75    \end{SUPPRESSEDENV}
    5576\item[Hardware Accelerators Synthesis (HAS):]
    5677    COACH will allow the automatic generation of hardware accelerators when required.
    5778    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
    5879    (ASIP) design environment and source-level transformation tools (loop transformations
    59     and memory optimisation) will be provided.
     80    and memory optimization) will be provided.
    6081    This will allow further exploration of the micro-architectural design space.
    6182    HLS tools are sensitive to the coding style of the input specification and the domain
     
    6889    dedicated coprocessors and ASIPs and by fixing template parameters such as
    6990    the number of embedded processors, the number of sizes of embedded memory banks
    70     or the embedded the operating system.
    71     However, the specification of the application will be independant of both the
     91    or the embedded operating system.
     92    However, the specification of the application will be independent of both the
    7293    architectural template and the target FPGA device.
    7394    Basically, the following three architectural templates will be provided:
     
    7798    \item An \altera architectural template based on the \altera IP core library, the
    7899      AVALON system bus and the NIOS processor.
    79     \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
     100    \item A \xilinx architectural template based on the \xilinx IP core library, the PLB
    80101      system bus and the Microblaze processor.
    81102    \end{enumerate}
     
    85106    communications between software tasks running on embedded processors and
    86107    dedicated hardware coprocessors.
     108\begin{ADDEDENV}
     109\item[Interaction with the industrial world]
     110    COACH will not be a closed framework but it will be opened to the industrial
     111    world by using the IP-XACT format \ref{IP-XACT-08} for describing the components of the
     112    architectural template and by providing the IP-XACT description of the generated MPSoC.
     113    This should facilitate the enhancement of the architectural template with IP and the
     114    integration of the IP produced by COACH in larger design.
     115\end{ADDEDENV}
    87116\end{description}
     117\begin{SUPPRESSEDENV}
     118MOVED ABOVE
    88119The COACH design flow will be dedicated to system designers, and will as
    89120much as possible hide the hardware characteristics to the end-user.
     121\end{SUPPRESSEDENV}
    90122%From the end user point of view, the specification of the application will be
    91123%independant from both the architectural template and from the selected FPGA
     
    102134MPSoC architectures (\tima, \ubs, \upmc),
    103135ASIP architectures (\irisa),
    104 High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
     136High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
     137HPC (\bull, \thales), \mustbecompleted{XXX (\mds)}.
    105138\\
    106139The COACH project does not start from scratch.
    107 It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).
     140\begin{SUPPRESSEDENV}
     141It strongly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
     142(DSX, component library), operating systems (MUTEKH, DNA/OS).
    108143It also leverages on  several existing technologies:
    109144on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
     
    111146on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
    112147and on the \xilinx and \altera IP core libraries.
    113 Finally it will use the \xilinx and \altera logic and physical synthesis tools to generate the FPGA configuration
    114 bitstreams.
     148\end{SUPPRESSEDENV}\begin{ADDEDENV}
     149It relies
     150on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
     151on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
     152on the ROMA~\cite{roma} project for ASIP,
     153on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
     154transformations,
     155on the \mustbecompleted{XXXX:magillem} for \mustbecompleted{XXXX:magillem},
     156and on the \xilinx and \altera IP core libraries.
     157\end{ADDEDENV}
     158Finally it will use the \xilinx and \altera logic and physical synthesis tools
     159to generate the FPGA configuration bitstreams.
    115160\parlf
    116161The COACH proposal has been prepared during one year by a technical working group
    117162involving the 5 academic partners (one monthly meeting from january 2009 to february
    1181632010). The objective was to analyse the issues of integrating
    119 and enhancing the existing tools and tecnnologies into a unique framework.
     164and enhancing the existing tools and technologies into a unique framework.
    120165Most of the general software architecture of the proposed design flow (including the
    121166exchange format specification) has been define by this working group.
    122 Because the COACH project leanes on the ANR SoCLib platform, it may be described as an
    123 extension of the SoCLib platform.
     167\SUPPRESSED{Because the COACH project leanes on the ANR SoCLib platform, it may be
     168described as an extension of the SoCLib platform.}
    124169%The main development steps of the COACH project are:
    125170%\begin{enumerate}
     
    146191a supporter (see letter page \pageref{supp:1})
    147192providing documentation and development boards. These two companies are strongly motivated
    148 to help the COACH project to generate efficient bitsreams for both FPGA families.
    149 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
     193to help the COACH project to generate efficient bitstreams for both FPGA families.
     194The role of the industrial partners \bull, \thales and \mds is to provide
    150195real use cases to benchmark the COACH design environment and to analyze the designer productivity
    151196improvements.
    152197\parlf
     198\begin{SUPPRESSEDENV}
    153199Following the general policy of the SoCLib platform, the COACH project will be an open
    154200infrastructure, available in the framework of the SoCLib server.
    155201The architectural templates, and the COACH software tools will be distributed under the
    156202GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
    157 IP core library) will be freely available for non commercial use. For industrial exploitation
    158 the technology providers are ready to propose commercial licenses, directly to the end user,
    159 or through a third party.
    160 \parlf
    161 Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the
     203IP core library) will be freely available for non commercial use.
     204\end{SUPPRESSEDENV}\begin{ADDEDENV}
     205The COACH project will be an open infrastructure and freely distributed.
     206The architectural templates and the COACH software tools will be distributed under the
     207GPL license. The VHDL synthesizable models for the neutral architectural template
     208will also be freely available for non commercial use.
     209\end{ADDEDENV}
     210For industrial exploitation the technology providers are ready to propose commercial licenses,
     211directly to the end user, or through a third party.
     212\parlf
     213\mustbecompleted{LIST NON A JOUR}
     214Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the
    162215"letters of interest" (see Annex B), that have collected during the preparation of the project :
    163216ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
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