Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 282) +++ /anr/anr.tex (revision 283) @@ -59,14 +59,13 @@ \def\ubs{LAB-STICC\xspace} \def\Subs{\Sformat{UBS}\xspace} \def\upmc{LIP6\xspace} \def\Supmc{\Sformat{LIP6}\xspace} +\def\bull{BULL\xspace} \def\Sbull{\Sformat{BULL}\xspace} +\def\thales{THALES\xspace} \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales +\def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace} + \def\altera{ALTERA\xspace} \def\Saltera{\Sformat{ALTE}\xspace} \def\xilinx{XILINX\xspace} \def\Sxilinx{\Sformat{XILX}\xspace} -\def\bull{BULL\xspace} \def\Sbull{\Sformat{BULL}\xspace} -\def\thales{THALES\xspace} \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales -\def\zied{FLEXRAS\xspace} \def\Szied{\Sformat{FLEX}\xspace} -\def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace} -\def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace} \def\alllabs{\irisa \citi \lip \tima \ubs \upmc} -\def\allcompagnies{\bull \thales \zied\xspace} +\def\allcompagnies{\bull \thales \mds\xspace} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -270,5 +269,5 @@ \Sirisa for \irisa, \Slip for \lip, \Stima for \tima, \Subs for \ubs, \Supmc for \upmc, \Sxilinx for \xilinx, \Sbull for \bull, \Sthales for \thales, - \Szied for \zied and \Snavtel for \navtel. + and \Smds for \mds. \item[kind of the deliverable] \texttt{x} for a software, \texttt{d} for a document and \texttt{h} for a hardware Index: /anr/section-5.tex =================================================================== --- /anr/section-5.tex (revision 282) +++ /anr/section-5.tex (revision 283) @@ -43,10 +43,10 @@ optimised cache controllers, peripheral controllers, or bus controllers. For non commercial use (i.e. research or education in an academic context, -or feasbility study in an industrial context), the synthesizable VHDL models will be freely available. -For commercial use, commercial licenses will be negociated between the owners and the customers. +or feasibility study in an industrial context), the synthesizable VHDL models will be freely available. +For commercial use, commercial licenses will be negotiated between the owners and the customers. \item -The proprietary \altera, \xilinx and \zied IP core libraries are commercial products +The proprietary \altera and \xilinx IP core libraries are commercial products that are not involved by the free software policy, but these libraries will be supported by the -synthesis tools developped in the COACH project. +synthesis tools developed in the COACH project. \end{itemize} @@ -57,4 +57,8 @@ \subsection{Indusrial Interest in COACH} +\subsubsection*{Partner: \textit{\mds}} + +\mustbecompleted{Emanuel ....} + \subsubsection*{Partner: \textit{\bull}} The team of \bull participating to the COACH project is from the Server Development @@ -63,14 +67,14 @@ FPGA parallelism) to add to existing Bull HPC solutions. -\subsubsection*{Partner: \textit{\xilinx}} -Computing power potential of our FPGA architectures -growing very quickly on one side, and complexity of designs implemented -using our FPGAs dramatically increasing on the other side, it is very -interesting for us to get high level design methodologies progressing -quickly and targetting our FPGAs in the most possible efficient way. -\parlf -\xilinx goal is to get COACH to generate bitstream optimized as much as possible for -\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease -future work of our customers. +%\subsubsection*{Partner: \textit{\xilinx}} +%Computing power potential of our FPGA architectures +%growing very quickly on one side, and complexity of designs implemented +%using our FPGAs dramatically increasing on the other side, it is very +%interesting for us to get high level design methodologies progressing +%quickly and targetting our FPGAs in the most possible efficient way. +%\parlf +%\xilinx goal is to get COACH to generate bitstream optimized as much as possible for +%\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease +%future work of our customers. \subsubsection*{Partner: \textit{\thales}} @@ -107,22 +111,7 @@ border monitoring. -\subsubsection*{Partner: \textit{\zied}} +\subsubsection*{Industrial supports} -\zied is developing a new architecture for embedded system. Our interest in using COACH -are: -\begin{itemize} - \item firstly, to validate our new architecture by emulating it with COACH. - \item Secondly, to use this emulator and the COACH potential to quickly setup - demonstrator to our customer. -\end{itemize} - -\subsubsection*{Partner: \textit{\navtel}} -\navtel has a platform for high performence computation based on ARM processor and FPGAs -that embedde coprocessors. Currently, the coprocessors are handmade and their designs -constitute an important part of our product cost. We have try free HLS tools to diminish -them but the quality of the generated designs was not sufficient to be useable. -So our interest in COACH is mainly the HLS tools. - -\subsubsection*{Industrial supports} +\mustbecompleted{NON A JOUR} The following SMEs demonstrate interest to the COACH project (see the "letters of interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will Index: /anr/section-6.1.tex =================================================================== --- /anr/section-6.1.tex (revision 282) +++ /anr/section-6.1.tex (revision 283) @@ -152,6 +152,6 @@ \parlf Even if the preferred dissemination policy for the COACH design flow will be the free -software policy, (following the SoCLib model), the SoC department is ready to support -start-ups : Six startup companies (including \zied) have been created by former +software policy, the SoC department is ready to support start-ups : +Six startup companies have been created by former researchers from the SoC department of LIP6 between 1997 and 2002. @@ -189,4 +189,9 @@ the fact of the increase of the architecture complexity and due to the use of FPGA component for low power applications. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\mds} + +\mustbecompleted{Emanuel ....} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -247,52 +252,2 @@ computing embedded systems. -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\zied} - -\zied is an innovative start-up specialized in the conception of configurable circuits -and the development of CAD tools. \zied provides a complete front-to-back-end generator -of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs. -\zied solution is based on a patented FPGA architecture delivering an unprecedented -level of logic density. This high capacity is accessible using a traditional RTL flow from -Verilog/VHDL synthesis all the way to bitstream generation. -\parlf -\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the -French National Competition for Business Startup and Innovative Technology in 2007 and -2009 in "emergence" and "creation" categories respectively. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\navtel} - -\navtel was created in 1994 to develop flexible systems based on FPGAs and currently -focuses on intelligent signal mining for knowlege based signal processing systems. -The company main activity covers the following domains: satellite communication, -aeronautics, imaging and security. -\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical -and imaging systems and 30\% to its own research programmes in collaboration with French -and international partners. -\parlf -The multi disciplinary technical team comprises 6 engineers for signal processing and -hardware development and one technician. -\parlf -\navtel has its own Ph.D program which includes in the past (classification technology -and MIMO for FPGA implementation) and currently the preparation of a project for remote -sensing with signal intelligence for satellite application. The company participates in -national and European level projects contributing to a strategic alliance between academic -and industrial partners.\\ -The current research covers particle filter applications for communication and RADAR, -Cognitive Radio, Satellite communication, embedded super computing and focuses on low -power algorithms for implementation in FPGA and soft computing. -\parlf -For manufacturing and industrialization, \navtel works with ISO certified partners. -The company clients include the CNES, Thal\`{e}s Alenia Space, Thal\`{e}s Communication, EADS, -Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase up to the -system delivery. -\begin{description} -\item[Recognitions:]\mbox{} -\begin{itemize} - \item HEC Challenge+ program for innovative projects (promotion 9) - \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg - \item Recognition by the French Senate for company creation during the - \og Semaine de l'entrepreneur \fg 2005. -\end{itemize} -\end{description}