Index: /anr/Makefile =================================================================== --- /anr/Makefile (revision 288) +++ /anr/Makefile (revision 289) @@ -2,13 +2,19 @@ # required to build anr.pdf SOURCES= anr.tex anr.bib anr.sty section-1.tex \ - section-2.tex section-2.1.tex section-2.2.tex \ - flow2.pdf section-3.1.tex section-3.2.tex \ - task-0.tex task-1.tex task-2.tex task-3.tex \ - task-4.tex task-5.tex task-6.tex \ - section-4.1.tex section-4.4.tex \ + section-2.tex section-issues.tex section-position.tex \ + flow2.pdf section-etat-de-art.tex section-objectif.tex \ + section-project-description.tex section-project-management.tex \ architecture-csg.pdf architecture-hls.pdf architecture-hpc.pdf \ dependence-task-h.pdf \ - section-4.2.tex section-5.tex \ - section-6.1.tex section-6.2.tex section-7.tex + task-0.tex task-1.tex task-2.tex task-3.tex \ + task-4.tex task-5.tex task-6.tex task-7.tex \ + section-project-task-schedule.tex \ + section-dissemination.tex \ + section-consortium-desc.tex \ + section-consortium-leader.tex \ + section-consortium-people.tex \ + section-ressources.tex \ + annexe-cv.tex \ + annexe-autre-participation.tex TABLES= \ Index: /anr/annexe-autre-participation.tex =================================================================== --- /anr/annexe-autre-participation.tex (revision 289) +++ /anr/annexe-autre-participation.tex (revision 289) @@ -0,0 +1,6 @@ +\anrdoc{Un tableau par partenaire (Cf. 5.3)\\ +Mentionner ici les projets en cours de réalisation soit au sein de programmes de +de l'ANR, soit auprÚs d'organismes, de fondations, à l'Union Européenne, etc +que ce soit comme coordinateur ou comme partenaire. Pour chacun, donner le nom de +l'appel à projets, le titre du projet et le nom du coordinateur.} + Index: /anr/annexe-cv.tex =================================================================== --- /anr/annexe-cv.tex (revision 289) +++ /anr/annexe-cv.tex (revision 289) @@ -0,0 +1,2 @@ +\anrdoc{1 page maximum par personne (Cf. 5.3).} + Index: /anr/anr.bib =================================================================== --- /anr/anr.bib (revision 288) +++ /anr/anr.bib (revision 289) @@ -83,5 +83,5 @@ @InProceedings{disydent05, - author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}}, + author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}}, title = {{Platform-based design from parallel C specifications}}, booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems}, Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 288) +++ /anr/anr.tex (revision 289) @@ -2,5 +2,5 @@ \usepackage[french,english]{babel} -%\usepackage[utf8x]{inputenc} +\usepackage[utf8x]{inputenc} \usepackage{times} \usepackage[T1]{fontenc} @@ -17,4 +17,5 @@ \usepackage{lscape} \geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=2cm} +\usepackage{hyperref} \usepackage{anr} @@ -45,5 +46,5 @@ \definecolor{rouge}{rgb}{1.0,0.2,0.2} \def\mustbecompleted#1{} -\def\parlf{\par\vspace*{1.0ex}} +\def\parlf{\noexpand\par\vspace*{1.0ex}} \def\ADDED#1{\textcolor{blue}{#1}} \newenvironment{ADDEDENV}{\color{blue}}{} @@ -72,7 +73,4 @@ \def\ST{sub-task\xspace} \def\STs{sub-tasks\xspace} -% FIXME \def\taskresponsable#1#2#3{\ifvmode\else\\\fi -% FIXME The coordinator of this task is #1 member of #2. -% FIXME The partners collaborating in this task are #3.\\} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -87,15 +85,4 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%\title{% -%\textbf{COACH:} -%\textbf{C}onception d'\textbf{A}rchitecture par -%\textbf{C}ompilation et synt\textbf{H}\`{e}se\\ -%\begin{normalsize} -%(Architecture design by compilation and synthesis)% -%\end{normalsize} -%} - %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \begin{document} @@ -104,5 +91,11 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % 1 -%\maketitle +\anrdoc{ +Ce document, hors annexes, ne doit pas dépasser 40 pages, corps de texte en +police de taille 11. Ce point constitue un critÚre de recevabilité de la +proposition de projet. Les propositions de projets ne satisfaisant pas aux +critÚres de recevabilité ne seront pas évaluées. +} + \def\boitecochee{\fcolorbox{black}{black}{\makebox(0.20,0.20){}}} \noindent @@ -148,16 +141,8 @@ % 1 \section{Executive summary} -\anrdoc{(2 pages maximum) Résumer la problématique que le projet propose -de résoudre, et comment cet objectif sera poursuivi (quelle approche -technique, etc.). \\ -Ce résumé devra démontrer l'originalité du projet notamment sur les points -suivants: -\begin{itemize} -\item les objectifs globaux, les verrous scientifiques et techniques, -\item le programme de travail, -\item les retombées scientifiques, techniques et économiques. -\end{itemize} -Ces éléments peuvent être recopiés dans les champs «résumés scientifiques» -du site de soumission.} +\anrdoc{Recopier le résumé utilisé dans le document administratif et financier +(dit document de soumission)\\ +De memoire, la taille etait donnee en mot nots, et on avait ete oblige +de raccourcir enormement.} \input{section-1} @@ -165,102 +150,50 @@ % 2 \pagefeed\section{Context and relevance to the call } -\anrdoc{(1 page maximum) Présentation générale du problème qu'il est -proposé de traiter dans le projet et du cadre de travail -(recherche fondamentale, industrielle ou développement expérimental).} +\anrdoc{A titre indicatif: de 5 à 10 pages pour ce chapitre\\ +Présentation générale du problÚme qu¿il est proposé de traiter dans le +projet et du cadre de travail (recherche fondamentale, industrielle ou +développement expérimental).} \input{section-2} % 2.1 -\pagefeed\subsection{Economic and societal issues} -\anrdoc{(2 pages maximum) Décrire le contexte économique, social, réglementaire -dans lequel se situe le projet en présentant une analyse des enjeux sociaux, -économiques, environnementaux, industriels. Donner si possible des arguments -chiffrés, par exemple, pertinence et portée du projet par rapport à la -demande économique (analyse du marché, analyse des tendances), analyse -de la concurrence, indicateurs de réduction de coûts, perspectives de -marchés (champs d'application, ...). Indicateurs des gains environnementaux, -cycle de vie.} -\input{section-2.1} +\pagefeed\subsection{Context, social and economic issues}\input{section-issues} % 2.2 -\pagefeed\subsection{Relevance of the proposal} -\anrdoc{(2 pages maximum) Préciser :\begin{itemize} -\item positionnement du projet par rapport au contexte développé précédemment: - vis- à-vis des projets et recherches concurrents, complémentaires ou - antérieurs, des brevets et standards... -\item positionnement du projet par rapport aux axes thématiques de l'appel - à projets. -\item positionnement du projet aux niveaux européen et international. -\end{itemize}} -\input{section-2.2} +\pagefeed\subsection{Position of the project}\input{section-position.tex} + +% 2.3 +\pagefeed\subsection{State of the Art}\input{section-etat-de-art} + +% 2.4 +\pagefeed\subsection{Objectives, originality and novelty of the project} +\input{section-objectif.tex} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % 3 -\section{Scientific and technical Description} +\section{Scientific and technical objectives / project description} +\anrdoc{A titre indicatif: de 8 à 12 pages pour ce chapitre, en fonction +du nombre de taches.} % 3.1 -\pagefeed\subsection{State of the Art} -\anrdoc{(3 pages maximum) écrire le contexte et les enjeux scientifiques -dans lequel se situe le projet en présentant un état de l'art national et -international dressant l'état des connaissances sur le sujet. Faire -apparaître d'éventuels résultats préliminaires. Inclure les références -bibliographiques nécessaires en annexe 7.1.} -\input{section-3.1} +\pagefeed\subsection{Scientific programme, project structure} +\input{section-project-description.tex} % 3.2 -\pagefeed\subsection{S \& T objectives, progress beyond the state of the art} -\anrdoc{(2 pages maximum) -Décrire les objectifs scientifiques/techniques du projet.\\ -Présenter l'avancée scientifique attendue. Préciser l'originalité et le -caractère ambitieux du projet.\\ -Détailler les verrous scientifiques et techniques à lever par la -réalisation du projet.\\ -Décrire éventuellement le ou les produits finaux développés à l'issue du -projet montrant le caractère innovant du projet.\\ -Présenter les résultats escomptés en proposant si possible des critères de -réussite et d'évaluation adaptés au type de projet, permettant d'évaluer -les résultats en fin de projet.\\ -Le cas échéant (programmes exigeant la pluridisciplinarité), démontrer -l'articulation entre les disciplines scientifiques.} -\input{section-3.2} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% 4 -\section{Scientific and technical objectives / project description} - -% 4.1 -\pagefeed\subsection{Scientific Programme, Project structure} -\anrdoc{(2 pages maximum) -Présentez le programme scientifique et justifiez la décomposition en tâches -du programme de travail en cohérence avec les objectifs poursuivis.\\ -Utilisez un diagramme pour présenter les liens entre les différentes tâches -(organigramme technique)\\ -Les tâches représentent les grandes phases du projet. Elles sont en nombre -limité.\\ -N'oubliez pas les activités et actions correspondant à la dissémination et -à la valorisation.} -\input{section-4.1} - -% 4.2 \pagefeed\subsection{Project management} -\anrdoc{(2 pages maximum) -Préciser les aspects organisationnels du projet et les modalités de -coordination (si possible individualisation d'une tâche coordination : cf. -tâche 0 du document de soumission A).} -\input{section-4.2} - -% 4.3 -\pagefeed\subsection{Description of the tasks} +\input{section-project-management.tex} + +% 3.3 +\pagefeed\subsection{Description by task} \label{task-description} -\anrdoc{(idéalement 1 ou 2 pages par tâche) -Pour chaque tâche, décrire:\begin{itemize} -\item les objectifs de la tâche et éventuels indicateurs de succès, -\item le responsable de la tâche et les partenaires impliqués (possibilité +\anrdoc{Pour chaque tâche, décrire:\begin{itemize} +\item les objectifs de la tâche et éventuels indicateurs de succÚs, +\item le responsable de la tâche et les partenaires impliqués (possibilité de l'indiquer sous forme graphique), -\item le programme détaillé des travaux par tâche, -\item les livrables de la tâche, -\item les contributions des partenaires (le «qui fait quoi»), -\item la description des méthodes et des choix techniques et de la manière -dont les solutions seront apportées, -\item les risques de la tâche et les solutions de repli envisagées. +\item le programme détaillé des travaux par tâche, +\item les livrables de la tâche, +\item les contributions des partenaires (le «qui fait quoi»), +\item la description des méthodes et des choix techniques et de la maniÚre +dont les solutions seront apportées, +\item les risques de la tâche et les solutions de repli envisagées. \end{itemize}} In this document, we use the following abbreviations in the tables and Gantt diagrams: @@ -305,94 +238,29 @@ \input{task-7} +% 3.4 \subsection{Tasks schedule, deliverables and milestones} -\anrdoc{(3 pages maximum)\begin{itemize} -\item Présenter sous forme graphique un échéancier des différentes tâches -et leurs dépendances (diagramme de Gantt par exemple). -\item Présenter un tableau synthétique de l'ensemble des livrables du -projet (numéro de tâche, date, intitulé, responsable). -\item Préciser de façon synthétique les jalons scientifiques et/ou -techniques, les principaux points de rendez-vous, les points bloquants ou -aléas qui risquent de remettre en cause l'aboutissement du projet ainsi que -les réunions de projet prévues.\end{itemize}} -\input{section-4.4.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\section{Dissemination and exploitation of results. - Management of intellectual property} -\anrdoc{(1 à 2 pages)\\ -Présenter les stratégies de valorisation des résultats : -\begin{itemize} -\item la communication scientifique; -\item la communication auprès du grand public; -\item la valorisation des résultats attendus; -\item les retombées scientifiques, techniques, industrielles, économiques, -\item la place du projet dans la stratégie industrielle des entreprises partenaires du projet -\item autres retombées (normalisation, information des pouvoirs publics, ...) -\item les échéances et la nature des retombées technico- économiques attendues -\item l'incidence éventuelle sur l'emploi, la création d'activités nouvelles. -\end{itemize} -Présenter les grandes lignes des modes de protection et d'exploitation des -résultats\\ -Pour les projets partenariaux organismes de recherche/entreprises, les -partenaires devront conclure, sous l'égide du coordinateur du projet, un -accord de consortium dans un délai de un an si le projet est retenu pour -financement.\\ -Pour les projets académiques, l'accord de consortium n'est pas obligatoire -mais fortement conseillé.} -\input{section-5.tex} +\input{section-project-task-schedule.tex} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Dissemination and exploitation of results. Intellectual property} +\input{section-dissemination.tex} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Consortium Description} +\anrdoc{A titre indicatif: de 2 à 5 pages pour ce chapitre, en fonction du +nombre de partenaires} \subsection{Partners description \& relevance, complementarity} -\anrdoc{(maximum 0,5 page par partenaire) Décrire brièvement chaque -partenaire et fournir ici les éléments permettant d'apprécier la -qualification des partenaires dans le projet (le « pourquoi qui fait quoi -»). Il peut s'agir de réalisations passées, d'indicateurs (publications, -brevets), de l'intérêt du partenaire pour le projet.\\ -Montrer la complémentarité et la valeur ajoutée des coopérations entre les -différents partenaires. L'interdisciplinarité et l'ouverture à diverses -collaborations seront à justifier en accord avec les orientations du -projet. (1 page maximum)} -\input{section-6.1.tex} +\input{section-consortium-desc.tex} \subsection{Relevant experience of the project coordinator} -\input{section-6.2.tex} +\input{section-consortium-leader.tex} + +\subsection{Qualification and contribution of each partner} +\input{section-consortium-people.tex} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Scientific justification for the mobilisation of the resources} -\anrdoc{On présentera ici la justification scientifique et technique des moyens -demandés dans le document de soumission A par chaque partenaire et -synthétisés à l'échelle du projet dans la fiche «Tableaux récapitulatifs» -du document de soumission A.\\ -Chaque partenaire justifiera les moyens qu'il demande en distinguant les -différents postes de dépenses.} -\def\ressourcehelp{\anrdoc{\begin{itemize} -\item Equipment: 1) Préciser la nature des équipements* et justifier le - choix des équipements. 2) Si nécessaire, préciser la part de financement - demandé sur le projet et si les achats envisagés doivent être complétés - par d'autres sources de financement. Si tel est le cas, indiquer le - montant et l'origine de ces financements complémentaires. - 3) Attention: Un devis sera demandé si le projet est retenu pour - financement. -\item Personnel costs - 1) Le personnel non permanent (thèses, post- doctorants,CDD...) - financé sur le projet devra être justifié. - 2) Fournir les profils des postes à pourvoir pour les personnels à - recruter (1/2 page maximum par type de poste) - 3) Pour les thèses, préciser si des demandes de bourse de thèse sont - prévues ou en cours, en préciser la nature et la part de financement - imputable au projet. -\item Subcontracting. Préciser: 1) la nature des prestations - 2) le type de prestataire. -\item Travel. Préciser: 1) les missions liées aux travaux d'acquisition - sur le terrain (campagnes de mesures), - 2) les missions relevant de colloques, congrès. -\item Expenses for inward billing (Costs justified by internal procedures -of invoicing). Préciser la nature des prestations -\item Other working costs. Toute dépense significative relevant de ce poste -devra être justifiée. -\end{itemize}}} -\input{section-7} +\input{section-ressources.tex} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -401,9 +269,13 @@ \section{Bibliography} %\subsection{References} -\anrdoc{Inclure la liste des références bibliographiques utilisées dans la -partie «Etat de l'art» et les références bibliographiques des +\anrdoc{Inclure la liste des références bibliographiques utilisées dans la +partie \og état de l'art\fg et les références bibliographiques des partenaires ayant trait au projet.} \bibliographystyle{plain} \bibliography{anr} + +\newpage\section{CV, resume}\input{annexe-cv.tex} + +\newpage\section{Staff involvement in other contracts}\input{annexe-autre-participation.tex} \end{document} Index: r/section-2.1.tex =================================================================== --- /anr/section-2.1.tex (revision 288) +++ (revision ) @@ -1,129 +1,0 @@ -\begin{table}\leavevmode\center -\begin{small}\begin{tabular}{|l|l|l|l|}\hline -Segment & 2010 & 2011 & 2012 \\\hline\hline -Communications & 1,867 & 1,946 & 2,096 \\ -High end & 467 & 511 & 550 \\\hline -Consumer & 550 & 592 & 672 \\ -High end & 53 & 62 & 75 \\\hline -Automotive & 243 & 286 & 358 \\ -High end & - & - & - \\\hline -Industrial & 1,102 & 1,228 & 1,406 \\ -High end & 177 & 188 & 207 \\\hline -Military/Aereo & 566 & 636 & 717 \\ -High end & 56 & 65 & 82 \\\hline\hline -Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ -Total High-End FPGA & 753 & 826 & 914 \\\hline -\end{tabular}\end{small} -\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} -\end{table} -% -Microelectronic components allow the integration of complex functions into products, increases -commercial attractivity of these products and improves their competitivity. -Multimedia and tele-communication sectors have taken advantage from microelectronics facilities -thanks to the developpment of design methodologies and tools for embedded systems. -Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design -and manufacturing ASICs is very high. -An IC foundry costs several billions of euros and the fabrication of a specific circuit -costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 -million USD. -Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium -volume markets. -\parlf -Today, FPGAs become important actors in the computational domain that was originally dominated -by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed -on a per-application basis. For many applications, FPGAs offer significant performance benefits over -microprocessors implementation. There is still a performance degradation of one order -of magnitude versus an equivalent ASIC implementations, but low cost -(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive -choice for low-to-medium volume applications. -Since their introduction in the mid eighties, FPGAs evolved from a simple, -low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that -provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, -on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement -complex systems like multi-processors platform with application dedicated coprocessors. -Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in -various application domains. The ``high end'' lines concern only FPGA with high logic -capacity for complex system implementations. -This market is in significant expansion and is estimated to 914\,M\$ in 2012. -%The HPC market size is estimated today by FPGA providers at 214\,M\$. -%Using FPGA limits the NRE costs to the design cost. -%This boosts the developpment of automatic design tools and methodologies. -% -\parlf -Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, -Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand -for very high performance (HPC) primes over other requirements. They tend to use the highest -performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative -architectures and algorithms. These companies show up in different "traditional" applications and market -segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC -emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers -at 214\,M\$. -This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion -of FPGA-based solutions is limited by the lack of design automation. -\\ -\\ -Nowadays, there are no commercial or academic tools covering the whole design flow -from the system level specification to the bitstream generation neither for embedded system design -nor for HPC. - -%PC => IA et Alain -%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue -%Je le mets donc en commentaire - -%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and -%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP, -%processor, bus core, ...) as well as incorporate their own IP. -%Designers can then generate a synthesized netlist, simulation test bench and custom -%software library that reflect the hardware configuration. -%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to -%simulate the platform at a high design level (systemC). -%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation -%tool to implement designs on \altera devices (Stratix, Arria, Cyclone). -%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize -%coprocessors from a C++ description. -%Nevertheless, they can only deal with data dominated applications and they do not handle -%the platform level. -%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to -%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs. -%Designers can design and simulate a system using MATLAB and Simulink. The tool will then -%automatically generate synthesizable Hardware Description Language (HDL) code mapped to -%\xilinx pre-optimized macro-cells. -%However, this tool targets only DSP based algorithms. -%\\ -%Consequently, a designer developping an embedded system needs to master four different -%design environments: -%\begin{enumerate} -% \item a virtual prototyping environment such as SoCLib for system level exploration, -% \item an architecture compiler (such as SOPC Builder from \altera, or System generator -% from \xilinx) to define the hardware architecture, -% \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for -% coprocessor synthesis, -% \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation. -%\end{enumerate} -%Furthermore, mixing these tools requires an important interfacing effort and this makes -%the design process very complex and achievable only by designers skilled in many domains. - -\begin{center}\begin{minipage}{.9\linewidth}\textit{ -The aim of the COACH project is to integrate all these design steps into a single design framework -and to allow \textbf{pure software} developpers to design embedded systems. -}\end{minipage}\end{center} - -%PC => IA et Alain -% le paragraphe suivant est coupé collé de la section suivante 2.2 - - -\parlf -The COACH project proposes an open-source framework for mapping multi-tasks software applications -on Field Programmable Gate Array circuits (FPGA). -It aims to propose solutions to the societal/economical challenges by -providing SMEs novel design capabilities enabling them to increase their -design productivity with design exploration and synthesis methods that are placed on top -of the state-of-the-art methods. -We believe that the combination of a design environment dedicated to software developpers -and FPGA targets, -will allow small and even very small companies to propose embedded system and accelerating solutions -for standard software applications with attractive and competitive prices. -This new market may explode in the same way as the micro-computer market in the eighties, -whose success was due to the low cost of the first micro-processors (compared to main frames) -and the advent of high level programming languages which allowed a high number of programmers -to launch start-ups in software engineering. Index: r/section-2.2.tex =================================================================== --- /anr/section-2.2.tex (revision 288) +++ (revision ) @@ -1,221 +1,0 @@ -% Relevance of the proposal -%The COACH proposal addresses directly the \emph{Embedded Systems} item of -%the ARPEGE program. - -%PC => IA et ALain -%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1 - -%It aims to propose solutions to the societal/economical challenges by -%providing SMEs novel design capabilities enabling them to increase their -%design productivity with design exploration and synthesis methods that are placed on top -%of the state-of-the-art methods. -%This project proposes an open-source framework for mapping multi-tasks software applications -%on Field Programmable Gate Array circuits (FPGA). -%%% -\parlf -COACH will contribute to build an open design and run-time -environment, including communication middleware and tools to support -developers in the production of embedded software, through all phases of the software lifecycle, -from requirements analysis downto deployment and maintenance. -More specifically, COACH focuses on: -\begin{itemize} -\item High level methods and concepts (esp. requirements and architectural level) for system -design, development and integration, addressing complexity aspects and modularity. -\item Open and modular design environments, enabling flexibility and extensibility by -means of new or sector-specific tools and ensuring consistency and traceability along the -development lifecycle. -\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive -environment, suitable for co-operative and distributed development. -\end{itemize} -COACH outcome will contribute to strengthen Europe's competitive position by developing -technologies and methodologies for product design, focusing (in compliance with the -%scope of the above program) on technologies, engineering methodologies, novel tools, -%methods which facilitate resource use efficiency. The approaches and tools to be developed -%in COACH will enable new and emerging information technologies for the development, -%methods which facilitate resource use efficiency. The COACH approaches and tools -scope of the above program) on technologies, engineering methodologies, novel tools -which facilitate resource use efficiency. The COACH approaches and tools -will enable new and emerging information technologies for the development, -manufacturing and integration of devices and related software into end-products. -%%% -\parlf\noindent -The COACH project will benefit from a number of previous recent projects: -\begin{description} - \item[SOCLIB] - The SoCLib ANR platform (2007-2009) is an open infrastructure developped by - 10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 - industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). - It supports system level virtual prototyping of shared memory, multi-processors - architectures, and provides tools to map multi-tasks software application on these - architectures, for reliable performance evaluation. - The core of this platform is a library of SystemC simulation models for - general purpose IP cores such as processors, buses, networks, memories, IO controller. - The platform provides also embedded operating systems and software/hardware - communication middleware. - The synthesisable VHDL models of IPs are not part of the SoCLib platform, and - COACH will enhance SoCLib by providing the synthesisable VHDL models required - for FPGA synthesis. - \item[ROMA] The ROMA ANR project \cite{roma} - involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D, - proposes to develop a reconfigurable processor, exhibiting high - silicon density and power efficiency, able to adapt its computing - structure to computation patterns that can be speed-up and/or - power efficient. %The ROMA project study a pipeline of - %evolved low-power coarse grain reconfigurable operators to avoid - %traditional overhead, in reconfigurable devices, related to the - %interconnection network. - The project will borrow from the ROMA - ANR project and the ongoing joint INRIA-STMicro - Nano2012 project to adapt existing pattern extraction algorithms - and datapath merging techniques to ASIP synthesis. -% and datapath merging techniques to the synthesis of customized -% ASIP processors. - \item[TSAR] - The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a -% The TSAR MEDEA+ project (2008-2010) targets the design of a - scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib - plaform for virtual prototyping. COACH will benefit from the synthesizable VHDL - models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). - \item[BioWic] - On the HPC application side, we also hope to benefit from the experience in - hardware acceleration of bioinformatic algorithms/workfows gathered by the - CAIRN group in the context of the ANR BioWic project (2009-2011), so as to - be able to validate the framework on real-life HPC applications. -\end{description} -%%% -\parlf\noindent -The laboratories involved in the COACH project have a well estabished expertise -%in the following domains: -in the domains: -\begin{itemize} - \item - In the field of High Level Synthesis (HLS), the project - leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project - developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped - by the \upmc and \tima laboratories. - \item - Regarding system level architecture, the project is based on the know-how - acquired by \upmc and \tima in the framework of various projects - in the field of communication architectures for shared memory multi-processors systems - (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA). - As an example, the DSPIN project is now used in the TSAR project. - \item - Regarding Application Specific Instruction Processor (ASIP) design, the - CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of - expertise in the domain of retargetable compiler - (Armor/Calife~\cite{CODES99} since 1996, and the Gecos - compilers~\cite{ASAP05} since 2002). -\item - In the field of compilers, the \lip Compsys group was founded in 2002 - by several senior researchers with experience in - high performance computing and automatic parallelization. They have been - among the initiators of the polyhedral model, a theory which serve to - unify many parallelism detection and exploitation techniques for regular - programs. It is expected that the techniques developped by \lip for - parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb}, - process construction \cite{Feau:96} and memory management \cite{bee} - will be very useful as a front-end for HLS tools. -\end{itemize} -%%% -\parlf\noindent -The COACH project answers to several of the challenges found in different axis of the -call for proposals.%Keywords of the call are indicated below in italic writing. -\begin{description} -\item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\ -COACH will address new embedded systems architectures by allowing the design of -Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design -constraints and objectives (real-time, low-power). It will permit designing complex SoC -based on IP cores (memory, peripherals...), -running Embedded Software, as well as an Operating System with associated middleware and -API and using hardware accelerator automatically generated. It will also permit to use -efficiently different dynamic system management techniques and re-configuration mechanisms. -\textbf{Thereby COACH well corresponds to axis 1}. -% -\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\ -COACH will address High-Performance Computing (HPC) by helping designers to accelerate an -application running on a PC. -By providing tools that translate high level language programs to FPGA -configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the -PC bus (through a communication link like PCI/X). -Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance -as well as reducing the required area. -\textbf{Thereby COACH partially corresponds to axis 2}. -% -% IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et -% IA2PC: secondaire. -%VERS 3 -%\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\ -%Manufacturing technology employs more and more SoC. -%COACH will permit to design such complex digital systems. -%\textbf{Thereby COACH indirectly answers to axis 3 too}. - - -%\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\ -%VERS 1 -%Future control applications employ more and more SoC. -%Application domains for such systems are for example the automotive domain, as well as the -%aerospace and avionics domains. -%In all cases, high performance and real time requirements are combined with -%requirements to low power, low temperature, high dependability, and low cost.\\ -%Similary manufacturing, security and safety technologies require also more and more -%computation power. -%VERS 2 pour gagner de la place -%Manufacturing, controling, security and safety technologies employ more and more SoC. -%COACH will permit to design such complex digital systems. -%\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}. - -%\end{description} - -\item [Axis 3] \textit {Robotique et contr\^{o}le/commande}: - -COACH will address robotic and control applications by -allowing to design complex systems based on MPSoC architecture. -Like in the consumer electronics domain, future control applications -will employ more and more SoC for safety and security applications. -Application domains for such systems are for example automotive -or avionics domains (e.g. collision-detection, intelligent navigation...). -Manufacturing technology will also increasingly need high-end vision analysis and high-speed -robot control. -\textbf{Thereby COACH indirectly answers to axis 3}. - -\item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}: - -The results of the COACH project will help users to build cryptographic secure systems implemented in -hardware or both in software/hardware in an effective way, substantially enhancing the -process productivity of the cryptographic algorithms hardware synthesis, improving the -quality and reducing the design time and the cost of synthesised cryptographic devices. -\textbf{Thereby COACH indirectly answers to axis 5}. - -\end{description} - -% IA2PC: 1) je ne vois pas trop ce que ca fait la. -% IA2PC: 2) c'est deja dans le 2.1 pour le small business. -% IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense -% IA2PC toujours que le large business est encore vise par COACH. -% IA2PC Alain a enleve toute reference sur ce large business. Sa raison est + -% IA2PC politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille -% IA2PC le message. Je partage assez son avis, la version actuelle est + claire que -% IA2PC celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses -% IA2PC boites. -% IA2PC -% IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large -% IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans -% IA2PC les sections precedentes. -% -% VERS 2 pour gagner de la place je l'enleve - -%PC2IA ok pas de probleme - -% COACH technologies can be used in both large and small business, as they will permit users to design -% embedded systems which meet a wide range of requirements: from low cost and low power consuming -% devices to very high speed devices, based on parallel computing. For enterprises that will use embedded -% systems designed via the approaches and tools targeted by COACH, there is the potential for greater -% efficiency, improved business processes and models. The net results: lower costs, faster response times, -% better service, and higher revenue. -%\parlf -Finally, it is worth to note that this project covers priorities defined by the commission -experts in the field of Information Technolgies Society (IST) for Embedded -Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity -and allowing to apply efficiently applications and various products on embedded platforms, -considering resources constraints (delays, power, memory, etc.), security and quality -services$>>$}. Index: r/section-3.1.tex =================================================================== --- /anr/section-3.1.tex (revision 288) +++ (revision ) @@ -1,230 +1,0 @@ -% vim:set spell: -% vim:spell spelllang=en: - -Our project covers several critical domains in system design in order -to achieve high performance computing. Starting from a high level description we aim -at generating automatically both hardware and software components of the system. - -\subsubsection{High Performance Computing} -% Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language -The High-Performance Computing (HPC) world is composed of three main families of architectures: -many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA. -The first two families are dominating the market by taking benefit -of the strength and influence of mass-market leaders (Intel, Nvidia). -%such as Intel for many-core CPU and Nvidia for GPGPU. -In this market, FPGA architectures are emerging and very promising. -By adapting architecture to the software, % (the opposite is done in the others families) -FPGAs architectures enable better performance -(typically between x10 and x100 accelerations) -while using smaller size and less energy (and heat). -However, using FPGAs presents significant challenges~\cite{hpc06a}. -First, the operating frequency of an FPGA is low compared to a high-end microprocessor. -Second, based on Amdahl law, HPC/FPGA application performance is unusually sensitive -to the implementation quality~\cite{hpc06b}. -% Thus, the performance strongly relies on the detected parallelism. -% (pour résumer les 2 derniers points) -Finally, efficient design methodology are required in order to -hide FPGA complexity and the underlying implantation subtleties to HPC users, -so that they do not have to change their habits and can have equivalent design productivity -than in others families~\cite{hpc07a}. - -%état de l'art FPGA -HPC/FPGA hardware is only now emerging and in early commercial stages, -but these techniques have not yet caught up. -Industrial (Mitrionics~\cite{hpc08}, Gidel~\cite{hpc09}, Convey Computer~\cite{hpc10}) and academic (CHREC) -researches on HPC-FPGA are mainly conducted in the USA. -None of the approaches developed in these researches are fulfilling entirely the -challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator, -but extension generation is not automated and requires hardware design skills. -Mitrionics has an elegant solution based on a compute engine specifically -developed for high-performance execution in FPGAs. Unfortunately, the design flow -is based on a new programming language (mitrionC) implying important designer efforts and poor portability. -% tool relying on operator libraries (XtremeData), -% Parle t-on de l'OPenFPGA consortium, dont le but est : "to accelerate the incorporation of reconfigurable computing technology in high-performance and enterprise applications" ? - -Thus, much effort is required to develop design tools that translate high level -language programs to FPGA configurations. -Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12} -(DPR, which enables changing a part of the FPGA, while the rest is still working) -appears very interesting for improving HPC performance as well as reducing required area. - -\subsubsection{System Synthesis} -Today, several solutions for system design are proposed and commercialized. -The existing commercial or free tools do not -cover the whole system synthesis process in a full automatic way. Moreover, -they are bound to a particular device family and to IPs library. -The most commonly used are provided by \altera and \xilinx to promote their -FPGA devices. These representative tools used to synthesize SoC on FPGA -are introduced below. -\\ -The \xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a -plug-in to Simulink that enables designers to develop high-performance DSP -systems for \xilinx FPGAs. -Designers can design and simulate a system using MATLAB and Simulink. The -tool will then automatically generate synthesizable Hardware Description -Language (HDL) code mapped to \xilinx pre-optimized algorithms. -However, this tool targets only DSP based algorithms, \xilinx FPGAs and -cannot handle a complete SoC. Thus, it is not really a system synthesis tool. -\\ -In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx -Platform Studio XPS from \xilinx allows to describe a system, to synthesis it, -to program it into a target FPGA and to upload a software application. -Both SOPC Builder and XPS, allow designers to select and parameterize components from -an extensive drop-down list of IP cores (I/O core, DSP, processor, bus core, ...) -as well as incorporate their own IP. Nevertheless, all the previously introduced tools -do not provide any facilities to synthesize coprocessors and to simulate the platform -at a high level (SystemC). -System designer must provide the synthesizable description of its own IP-cores with -the feasible bus interface. Design Space Exploration is thus limited -and SystemC simulation is not possible neither at transactional nor at cycle -accurate level. -\\ -In addition, \xilinx System Generator, XPS and SOPC Builder are closed world -since each one imposes their own IPs which are not interchangeable. -Designers can then only generate a synthesized netlist, VHDL/Verilog simulation test -bench and custom software library that reflect the hardware configuration. - -Consequently, a designer developing an embedded system needs to master four different -design environments: -\begin{enumerate} - \item a virtual prototyping environment (in SystemC) for system level exploration, - \item an architecture compiler to define the hardware architecture (Verilog/VHDL), - \item one or several third-party HLS tools for coprocessor synthesis (C to RTL), - \item and finally back-end synthesis tools for the bit-stream generation (RTL to bitstream). -\end{enumerate} -Furthermore, mixing these tools requires an important interfacing effort and this makes -the design process very complex and achievable only by designers skilled in many domains. - -\subsubsection{High Level Synthesis} -High Level Synthesis translates a sequential algorithmic description and a -set of constraints (area, power, frequency, ...) to a micro-architecture at -Register Transfer Level (RTL). -Several academic and commercial tools are today available. The most common -tools are SPARK~\cite{spark04}, GAUT~\cite{gaut08}, UGH~\cite{ugh08} in the -academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and -CYNTHETIZER~\cite{cynthetizer} in the commercial world. Despite their -maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}: -\begin{itemize} -\item HLS tools are not integrated into an architecture and system exploration tool. -Thus, a designer who needs to accelerate a software part of the system, must adapt it manually -to the HLS input dialect and perform engineering work to exploit the synthesis result -at the system level, -\item Current HLS tools can not target control AND data oriented applications, -\item HLS tools take into account mainly a unique constraint while realistic design -is multi-constrained. -Low power consumption constraint which is mandatory for embedded systems is not yet -well handled or not handled at all by the HLS tools already available, -\item The parallelism is extracted from initial specification. -To get more parallelism or to reduce the amount of required memory in the SoC, the user -must re-write the algorithmic specification while there is techniques such as polyedric -transformations to increase the intrinsic parallelism, -\item While they support limited loop transformations like loop unrolling and loop -pipelining, current HLS tools do not provide support for design space exploration neither -through automatic loop transformations nor through memory mapping, -\item Despite having the same input language (C/C++), they are sensitive to the style in -which the algorithm dis written. Consequently, engineering work is required to swap from -a tool to another, -\item They do not respect accurately the frequency constraint when they target an FPGA device. -Their error is about 10 percent. This is annoying when the generated component is integrated -in a SoC since it will slow down the whole system. -\end{itemize} -Regarding these limitations, it is necessary to create a new tool generation reducing the gap -between the specification of an heterogeneous system and its hardware implementation \cite{HLSBOOK} \cite{IEEEDT}. - -\subsubsection{Application Specific Instruction Processors} - -ASIP (Application-Specific Instruction-Set Processor) are programmable -processors in which both the instruction and the micro architecture have -been tailored to a given application domain or to a -specific application. This specialization usually offers a good compromise -between performance (w.r.t a pure software implementation on an embedded -CPU) and flexibility (w.r.t an application specific hardware co-processor). -In spite of their obvious advantages, using/designing ASIPs remains a -difficult task, since it involves designing both a micro-architecture and a -compiler for this architecture. Besides, to our knowledge, there is still -no available open-source design flow for ASIP design even if such a tool - would be valuable in the -context of a System Level design exploration tool. -\par -In this context, ASIP design based on Instruction Set Extensions (ISEs) has -received a lot of interest~\cite{NIOS2}, as it makes micro architecture synthesis -more tractable \footnote{ISEs rely on a template micro-architecture in which -only a small fraction of the architecture has to be specialized}, and help ASIP -designers to focus on compilers, for which there are still many open -problems\cite{ARC08}. -This approach however has a severe weakness, since it also significantly reduces -opportunities for achieving good speedups (most speedups remain between 1.5x and -2.5x), since ISEs performance is generally tied down by I/O constraints as -they generally rely on the main CPU register file to access data. - -% ( -%automaticcaly extraction ISE candidates for application code \cite{CODES04}, -%performing efficient instruction selection and/or storage resource (register) -%allocation \cite{FPGA08}). -To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of -micro-architectural ISE models in which the coupling between the processor micro-architecture -and the ISE component is tightened up so as to allow the ISE to overcome the register -I/O limitations. However these approaches generally tackle the problem from a compiler/simulation -point of view and do not address the problem of generating synthesizable representations for -these models. - -We therefore strongly believe that there is a need for an open-framework which -would allow researchers and system designers to : -\begin{itemize} -\item Explore the various level of interactions between the original CPU micro-architecture -and its extension (for example through a Domain Specific Language targeted at micro-architecture -specification and synthesis). -\item Retarget the compiler instruction-selection pass -(or prototype new passes) so as to be able to take advantage of this ISEs. -\item Provide a complete System-level Integration for using ASIP as SoC building blocks -(integration with application specific blocks, MPSoc, etc.) -\end{itemize} - -\subsubsection{Automatic Parallelization} - -The problem of compiling sequential programs for parallel computers -has been studied since the advent of the first parallel architectures -in the 1970s. The basic approach consists in applying program transformations -which exhibit or increase the potential parallelism, while guaranteeing -the preservation of the program semantics. Most of these transformations -just reorder the operations of the program; some of them modify its -data structures. Dependences (exact or conservative) are checked to guarantee -the legality of the transformation. - -This has lead to the invention of many loop transformations (loop fusion, -loop splitting, loop skewing, loop interchange, loop unrolling, ...) -which interact in a complicated way. More recently, it has been noticed -that all of these are just changes of basis in the iteration domain of -the program. This has lead to the introduction of the polyhedral model -\cite{FP:96,DRV:2000}, in which the combination of two transformations is -simply a matrix product. - -Since hardware is inherently parallel, finding parallelism in sequential -programs in an important prerequisite for HLS. The large FPGA chips of -today can accomodate much more parallelism than is available in basic blocks. -The polyhedral model is the ideal tool for finding more parallelism in -loops. - -As a side effect, it has been observed that the polyhedral model is a useful -tool for many other optimization, like memory reduction and locality -improvement. Another point is -that the polyhedral domain \emph{stricto sensu} applies only to -very regular programs. Its extension to more general programs is -an active research subject. - -%\subsubsection{High Performance Computing} -%Accelerating high-performance computing (HPC) applications with field-programmable -%gate arrays (FPGAs) can potentially improve performance. -%However, using FPGAs presents significant challenges~\cite{hpc06a}. -%First, the operating frequency of an FPGA is low compared to a high-end microprocessor. -%Second, based on Amdahl law, HPC/FPGA application performance is unusually sensitive -%to the implementation quality~\cite{hpc06b}. -%Finally, High-performance computing programmers are a highly sophisticated but scarce -%resource. Such programmers are expected to readily use new technology but lack the time -%to learn a completely new skill such as logic design~\cite{hpc07a} . -%\\ -%HPC/FPGA hardware is only now emerging and in early commercial stages, -%but these techniques have not yet caught up. -%Thus, much effort is required to develop design tools that translate high level -%language programs to FPGA configurations. - Index: r/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 288) +++ (revision ) @@ -1,117 +1,0 @@ -% les objectifs scientifiques/techniques du projet. -The design steps are presented figure~\ref{coach-flow}. -\ADDED{ -The end-user input is -either a HPC application (an application running on a PC that must be accelarate), -or an embedded application (a standalone application), -or a sub-system application of a larger design. -The figure shows that the design flow of embedded and sub-system applications does not differ -except in the generation step and that the design flow of HPC application just adds a -preliminary step. -} -\begin{figure}[hbtp]\leavevmode\center - \includegraphics[width=1.0\linewidth]{flow2} - \caption{\label{coach-flow} COACH design flow} -\end{figure} -\begin{description} -\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application -which remains on the PC and the SoC application which is mapped on the FPGA. -COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) -which will allow performance evaluation. -\item[SoC design:] In this phase, -COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. -The user input will consist of a process network describing the coarse grain parallelism -of the application, an instance of an architectural template -and a mapping of processes on the architectural template components. -COACH will offer different targets to map the processes: -software (the process runs as a software task on a SoC processor), -ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), -and hardware (the process is implemented as a synthesized hardware coprocessor). -\begin{SUPPRESSEDENV} -\item[Application compilation:] -Once the SoC architecture is validated through performances analysis, -COACH will generate automatically an executable containing the host application and -the FPGA bitstream. This bitstream contains -both the hardware architecture and the SoC application software. -The user will be able to launch the application by -loading the bitstream on an FPGA and running the executable on PC. -\end{SUPPRESSEDENV}\begin{ADDEDENV} -\item[Generation:] -Once the SoC architecture is validated through performances analysis, -COACH generates its bitstream in the case of HPC or embedded application, -or its IP-XACT description for its integration in the case of a sub-system application. -Both descriptions contain the hardware architecture and the application software. -Furthermore in the HPC case, an executable containing the host application is -also generated and the user will be able to launch the application by loading -the bitstream on an FPGA and running the executable on PC. -\end{ADDEDENV} -\end{description} - -% l'avancee scientifique attendue. Preciser l'originalite et le caractere -% ambitieux du projet. -%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire} - -%The main scientific contribution of the project is to unify various synthesis techniques -%(same input and output formats) allowing the user to swap without engineering effort -%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis. -%Another advantage of this framework is to provide different abstraction levels from -%a single description. -%Finally, this description is device family independent and its hardware implementation -%is automatically generated. - -% Detailler les verrous scientifiques et techniques a lever par la realisation du projet. -Hardware/Software co-design is a very complex task. To simplify it, COACH will address the -following scientific and technological barriers: -\begin{description} -\item[\textit{Design Space Exploration by Virtual Prototyping}]: - The COACH environment will allow to easily map a parallel application (formally described as - an abstract network of process and communication channels) - COACH will permit the system designer to explore the design space, and to define the best - hardware/software partitioning of the application. -\item[\textit{Integration of system level modeling and HLS tools}]: - COACH will support the automated generation of hardware accelerators when required - by using High-Level Synthesis (HLS) tools. These HLS tools will be - fully integrated into a complete system-level design environment. - Moreover, COACH will support both data and control dominated applications, - and the HLS tools of COACH will support a common language and coding style - to avoid re-engineering by the designer. - COACH will provide a tool which will automatically explore the micro-architectural - design space of coprocessor. -\item[\textit{High-level code transformation}]: - COACH will allow to optimize the memory usage, to enhance the parallelism through - loop transformations and parallelization. The challenge is to identify the coarse - grained parallelism and to generate, - from a sequential algorithm, application containing multiple communicating - tasks. COACH will adapt techniques which were developed in the 1990 for - the construction of distributed programs. However, in the context of HLS, there are - several original problems to be solved, related to the FIFO communication channels and with - memory optimization. - COACH will support code transformation by providing a source to source C2C tool. -\item[\textit{Unified Hardware/Software communication middleware}]: - COACH will rely on he SoCLib experience to implement an unified hardware/software communication - infrastructure and communication APIs (Application Programming Interface), to support - communications between software tasks running on embedded processors and dedicated - hardware coprocessors. The main issue here is to support easy migration - from a software implementation to an hardware implementation. -\item[\textit{Processor customization}]: - ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. - COACH will allow system designers to explore the various level of interactions between - the original CPU micro-architecture and its extension. It will also allow to retarget - the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis - in a complete System-level design framework. -\end{description} - -%Presenter les resultats escomptes en proposant si possible des criteres de reussite -%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en -%fin de projet. -The main result is the framework. It is composed concretely of: -a communication middleware for HPC, -5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, -Memory optimization HLS and ASIP), -3 architectural templates that are synthesizable and that can be prototyped, -one design space exploration tool, -1 operating systems (DNA/OS). -\\ -The framework functionalities will be demonstrated with the demonstrators -(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 -page~\ref{subtask-tutorial}). Index: r/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 288) +++ (revision ) @@ -1,140 +1,0 @@ -\begin{figure}\leavevmode\center -\includegraphics[width=.8\linewidth]{architecture-csg} -\caption{\label{archi-csg} Software architecture for digital system generation} -%\end{figure}\begin{figure}\leavevmode\center -\mbox{}\vspace*{1ex}\\ -\includegraphics[width=1.0\linewidth]{architecture-hls} -\caption{\label{archi-hls} Software architecture of hardware accellerator synthesis} -%\end{figure}\begin{figure}\leavevmode\center -\mbox{}\vspace*{1ex}\\ -\includegraphics[width=.8\linewidth]{architecture-hpc} -\caption{\label{archi-hpc} Performance analysis of a HPC partitionning} -\end{figure} -% -Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} -summarize the software architecture of the COACH framework we will develop. -In figures, the dotted boxes are the softwares or formats that COACH -has to provide and to support. -\parlf -For the system generation presented in figure~\ref{archi-csg}, the conductor -is the tool \verb!CSG! (COACH System Generator). Its inputs are a process -network describing the target application and the synthesis parameters. -The main parameters are the target hardware architectural template -with its instantiation parameters, the hardware/software mapping of the -tasks, the FPGA device and design constraints. -\verb+CSG+ thus requires an architectural template library, an operating system -library, two system hardware component (CPU, memories, BUS...) libraries -(one for synthesis, one for simulation). -For generating the coprocessor of a task mapped as hardware, \verb+CSG+ -controls the HAS tools described below. -From these inputs \verb!CSG! can generate the entire system (both software and -hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger -design or} -as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the -design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and -launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the -FPGA device\footnote{Additional partial bitstreams are generated in case of - dynamic partial reconfiguration}. - \begin{ADDEDENV} - \\ - Furthermore the architecture template and hardware component libraries will be described - under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other - architecture or the enhancement of existing template with IP. - \end{ADDEDENV}% -\parlf -The software architecture for HAS is presented in figure~\ref{archi-hls}. -The input is a single task of the process network. The HAS tools do not work -directly on the C++ task description but on an internal format called -\xcoach generated by a plugin into the GNU C compiler (GCC). -This will allow on the one hand to insure that all the tools will -accept the same C++ description and on the other hand make possible -their chaining. The front-end tools read a \xcoach description and generate -a new \xcoach description that exibits more parallelism or implement -specific instructions for ASIP. The back-end tools read an \xcoach -description and generate an \xcoachplus description. This is an \xcoach -description annotated with hardware information (scheduling, binding) required by -the VHDL and systemC drivers. -Furthermore, the back-end tools uses a macro-cell library (functional and memory -unit). -\parlf -In addition to digital system design, HPC requires a supplementary -partitioning step presented in figure~\ref{archi-hpc}. The designer -splits the initial application (tag 1) in two parts: one still on the PC and the -other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data -through communication primitives (tag 2) implemented in a library. -To evaluate the relevance of the partitioning, the designer can build a -simulator. Once the partitioning is validated, the design of the FPGA part -is done through \verb!CSG! (figure~\ref{archi-csg}). -\parlf -The project is split into 8 tasks numbered from 1 to 8. They are described -in short below and in detail in section \ref{task-description}. -\begin{description} -\item[Task-1: \textit{Project management}] - This task relates to the monitoring of the COACH project. -\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the - project such as the defintion of the COACH inputs and outputs, - the internal formats (i.e. \xcoach and \xcoachplus) and their associated tools, - the architectural templates and the design flow. -\item[Task-3: \textit{System generation}] This task addresses the prototyping and - the generation of digital system. Apart from HAS that belongs to task 3 - and 4, its components are those presented figure~\ref{archi-csg} - (e.g. \verb!CSG!, operating systems). -\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities: - optimization of the memory usage, parallelism enhancement through loop - transformations, coarse grain parallelization and ASIP generation. -\item[Task-5: \textit{HAS back-end}] This task groups two functionalities: - High-Level Synthesis of data dominated description and HLS of control - dominated description. - This task contains also the development of a frequency adaptator - that will allow the coprocessors to respect the processor and the bus - frequency. -\item[Task-6: \textit{PC/FPGA communication middleware}] - This task pools the features dedicated to HPC. These are mainly the - validation of the partitioning (see figure~\ref{archi-hpc}), the sytem drivers for - both PC and FPGA-SoC sides, the hardware communication components and - the support for dynamic partial reconfiguration. -\item[Task-7: \textit{Industrial demonstrators}] - This task groups the demonstrators of the COACH project. - Most of them are industrial applications that will be developped within - the COACH framework. - Others consist in integrating the COACH framework as a driver of - industrial proprietary design tools. -\item[Task 8: \textit{Dissemination}] - This task concerns the diffusion of the project results. - It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!, - \verb!T0+24! and \verb!T0+36!), the publication of a tutorial and user manuals on a WEB site, the publication - of research papers in international journals and conferences and the organization of workshops and tutorials in - international conferences. -\end{description} -% -\begin{figure}\leavevmode\center -%\includegraphics[width=.4\linewidth]{dependence-task} -\includegraphics[width=0.70\linewidth]{dependence-task-h} -\caption{\label{dependence-task}Task dependencies} -\end{figure} -Figure~\ref{dependence-task} presents the tasks dependencies. -"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$. -The more bold the arrow, the more important is the impact. -The graph shows: -\begin{itemize} -\item Even though $T4$ and $T5$ functionalities are complementary, -their developments are independent (thanks to the \xcoach internal format). -\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may work -without $T4$ and $T5$ if targeted digital systems do not include hardware -accelerators. -\item $T3$ strongly impacts $T6$ but $T3$ does not depend at all on -$T6$. Hence demonstrators ($T7$) of embedded system would not be impacted if -$T6$ would fail. -\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) and is at the heart of -the COACH project. -\item The demonstrators developped in $T7$, of course strongly depend on the achievements -of the previous tasks ($T2$, $T3$, $T4$, $T5$, $T6$). -\item $T8$ and $T1$ depend on and impact all the other tasks. -\end{itemize} -This organisation offers enough robustness to insure the success of the -project except for the specification task $T2$. -The only critical task in this chart is $T2$. \label{xcoach-problem} -However, the partners met -12 times (a one-day meeting per month) during the last year: 10 meetings to exchange and work on scientific -and technical aspects and 2 meetings to prepare the project proposal. This gives us a high degree of confidence -that $T2$ will be completed in time. Index: r/section-4.2.tex =================================================================== --- /anr/section-4.2.tex (revision 288) +++ (revision ) @@ -1,67 +1,0 @@ -\begin{description} -\item[Project management structure] -Each task is assigned to a Task Leader. -The Task Leaders assist the project leader in the technical organization, effort -management, of the co-operation and the reporting of the progress. -A steering committee is composed by task leaders and the project leader. -The steering committee has a monthly conference call and is in charge of conflict -management if necessary. -Each task leader has to report on the main high-lights, major -opportunities and problems according to the work-plan. -The redaction of the 6-month reports is the responsability of the steering committee. -Therefore, each Partner has the responsibility to monthly inform the task Leaders of the -current development of the \ST he has in charge. -COACH will be organized in 8 tasks whose interactions are presented in -Figure~\ref{dependence-task}. - -\item[Scientific and Technical Reports] -For every yearly review, a written progress report for each deliverable has to be -provided by the task leader to the coordinator for integration in the contractual reports. - -\item[Management of knowledge, Intellectual Property Right (IPR) and Results Exploitation] -The partners will have to work under eventual NDA constraints. -Prior Intellectual Property remains property of the concerned partners. -The exploitation of the results obtained in the project and by each partner involved in the consortium will -follow the rules written in the articles of the Consortium Agreement accepted and signed by -each partner at most 6 months after the project kick-off. -To manage the exploitation and dissemination plan within the project, six -monthly meetings will analyze the intentions from the consortium (patent, publication...). - -\item[Management Tools] -In order to permit a good management, before the kick-off meeting, -each partner will have to identify (name, address, phone, fax and e-mail): -\begin{itemize} - \item the financial and administrative contact person, - \item the scientific and technical contact person, - \item all participants to the project. -\end{itemize} -A complete and detailed list will be communicated to each partner and to -the public Authority. The partners will construct mailing lists for -day-to-day communication. - -The first task will be the redaction of a Consortium Agreement, -dealing mainly with all aspects of the relations -between partners, including legal aspects, property rights and further -exploitation of the results. This document will be submitted to the -partner's financial and legal departments, and will define the management -rules (decision level, reporting systems, red flag cases). -A first draft of this document will be submitted to each partner -during the kick-off meeting. - -\item[Project follow-ups] -The basic communication between single project partners will be carried out by means of an Information System (web site), which will be developed and introduced at the very beginning of the project implementation. -All scientific and administrative data related to the project will be collected and -treated within a specific e-management plate-form accessible directly by the project web -site by an individual login and pass-word. -The web site will have a few levels of accessibility starting with completely free access, -open to broad public up to internal materials available only for members of the consortium -for the e-management area. -This communication tools will permit to perform all the reports and to follow as well as -possible all the tasks. - -\item[Project monitoring] -For this project format and size, a 12 months review by ANR, based on a yearly progress -report incorporating milestones reports and deliverables, seems optimum. -The internal consortium meetings will be every six months, including a kick-off meeting at the -start of the project, in our eyes the most important of all, as it phases the partners for the start of the project. -\end{description} Index: r/section-4.4.tex =================================================================== --- /anr/section-4.4.tex (revision 288) +++ (revision ) @@ -1,106 +1,0 @@ -\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90} -\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99} -\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7} -\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7} -\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4} -\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24} -\def\ganttlabelstyle#1{\begin{small}#1\end{small}} -\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}} - -%\begin{figure}\leavevmode\center -%\hspace*{-.6cm} -%\input{gantt.tex} -%\caption{\label{gantt}Gantt diagram of deliverables} -%\end{figure} - -\begin{figure}\leavevmode\center -\hspace*{-.4cm}%\vspace{-1.5cm} -\input{gantt1.tex} -\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)} -\end{figure} - -\begin{figure}\leavevmode\center -\hspace*{-.4cm}%\vspace{-1.5cm} -\input{gantt2.tex} -\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)} -\end{figure} - -The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project. -Before the final release (T0+36), there are 4 milestones (red lines on the figures) at -$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent -deliverables. -\begin{description} -\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of - the demonstatrors as a reference software. -\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are - written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC. - The main restrictions are: - 1) Only the neutral architectural template is supported, - 2) HAS is not available (but prototyping with virtual coprocessors is available), - 3) Enhanced communication schemes are not available. - 4) ASIP compilation flow is not available. -\item[Milestone 3 ($T0+18$)] The second COACH release. At this step most of the COACH - features are availables. A preliminary version of the ASIP synthesis flow is supported, for a - simple extensible MIPS model. The main restriction is that COACH can not yet - generate FPGA-SoC for \altera and \xilinx architectural templates. - The others restriction is that the HAS tools are not yet fully operational. -\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is - supported. - The main restriction are: - 1) The backend HAS tools have not been yet enhanced, - 2) Dynamic partial reconfiguration is not supported, - 3) NIOS processor instruction set extension is supported, but only for user specified patterns. -\item[Final Release ($T0+36$)] - -\end{description} -This organisation allows the project to globally progress step by step mixing development -and demonstrator deliverables. -Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility -at the integration phase is significantly reduced. -\par -The risks that have been identified at the beginning of the project are the following: -\begin{description} -\item[\xcoach format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})] - Partners have to agree on a convenient exchange format for all tools involved. - Because all the HAS tools rely on it, the \xcoach format specification is a - crucial step. There are no work-around but as mentionned in - section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it - for a full year and a preliminary document already exists. -%\item[\xcoachplus format (\novers{\specXcoachDoc}, -% \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] -% Its aim is the generation of the coprocessors (hardware \& prototyping model). -% By centralizing the coprocessor generation, it guarantees their functioning -% independently of the used HAS tools. -% Our experience with UGH and GAUT give us confidence in the succes of this -% task. -\item[Virtual prototyping of \altera \& \xilinx architectural templates (\novers{\csgImplementation})] - The SoCLib component library contains several SystemC models used for the virtual - prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores). - Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped. - If the workload of this simulation model development is too important, virtual prototyping - of those architectural templates will not be directly supported. - The three architectural templates being quite similar, the virtual - prototyping will use the neutral architectural template. -\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})] - If one of these tasks is impossible or too important or leads to inefficiency, - it will be abandoned. - In this case, the neutral architectural template will not be available for HPC and - a SystemC VCI model corresponding to the PCI/X IP will be developped to allow - virtual prototyping. -\end{description} -\parlf -Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}. -\begin{figure}\leavevmode\center -{ -\fontsize{7pt}{9pt}\selectfont -\settowidth\desclen{XILINX RTL optimisation (5)} -\def\Sformat#1{\textsc{#1}} -%\hspace*{-2.5mm} -\begin{minipage}{1.0\linewidth} -\input{table_livrable_01.tex} -\hfill\hspace*{1mm}\hfill -\input{table_livrable_02.tex} -\end{minipage} -} -\caption{\label{all-delivrables}All the deliverables} -\end{figure} Index: r/section-6.1.tex =================================================================== --- /anr/section-6.1.tex (revision 288) +++ (revision ) @@ -1,253 +1,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\inria/CAIRN} - -INRIA, the French national institute for research in computer science -and control, operating under the dual authority of the Ministry of -Research and the Ministry of Industry, is dedicated to fundamental and -applied research in information and communication science and -technology (ICST). The Institute also plays a major role in technology -transfer by fostering training through research, diffusion of -scientific and technical information, development, as well as -providing expert advice and participating in international programs. -\parlf -By playing a leading role in the scientific community in the field and -being in close contact with industry, INRIA is a major participant in -the development of ICST in France. Throughout its eight research -centres in Rocquencourt, Rennes, Sophia Antipolis, Grenoble, Nancy, -Bordeaux, Lille and Saclay, INRIA has a workforce of 3 800, 2 800 of -whom are scientists from INRIA and INRIA's partner organizations such -as CNRS (the French National Center for Scientific Research), -universities and leading engineering schools. They work in 168 joint -research project-teams. Many INRIA researchers are also professors and -approximately 1 000 doctoral students work on theses as part of INRIA -research project-teams. -%\parlf -%INRIA develops many partnerships with industry and fosters technology -%transfer and company foundation in the field of ICST - some ninety -%companies have been founded with the support of INRIA-Transfert, a -%subsidiary of INRIA, specialized in guiding, evaluating, qualifying, -%and financing innovative high-tech IT start-up companies. INRIA is -%involved in standardization committees such as the IETF, ISO and the -%W3C of which INRIA was the European host from 1995 to 2002. -%\parlf -%INRIA maintains important international relations and exchanges. In -%Europe, INRIA is a member of ERCIM which brings together research -%institutes from 19 European countries. INRIA is a partner in about 120 -%FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also -%collaborates with numerous scientific and academic institutions abroad -%(joint laboratories such as LIAMA, associated research teams, training -%and internship programs). - -The CAIRN group of INRIA Rennes -- Bretagne Atlantique study reconfigurable -system-on-chip, i.e. hardware systems whose configuration may change before or even during -execution. To this end, CAIRN has 13 permanent researchers and a variable number of PhD -students, post-docs and engineers. -CAIRN intends to approach reconfigurable architectures from three -angles: the invention of new reconfigurable platforms, the development -of associated transformation, compilation and synthesis tools, and the -exploration of the interaction between algorithms and architectures. -CAIRN is a joint team with CNRS, University of Rennes 1 and ENS Cachan. - -\subsubsection{\lip/Compsys} -The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team -of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du -Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers -and a variable number of PhD students and post-docs. Its field of -expertise is compilation for embedded system, optimizing compilers -and automatic parallelization. Its members were among the initiators -of the polyhedral model for automatic parallelization and program -optimization generally. It has authored or contributed to -several well known libraries for linear programming, polyhedra manipulation -and optimization in general. It has strong industrial cooperations, notably -with ST Microelectronics and \thales. - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\tima} -The TIMA laboratory ("Techniques of Informatics and Microelectronics -for integrated systems Architecture") is a public research laboratory -sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159), -Grenoble Institute of Technology (Grenoble-INP) and Universit\'{e} Joseph Fourier -(UJF). -The research topics cover the specification, design, verification, test, -CAD tools and design methods for integrated systems, from analog and -digital components on one end of the spectrum, to multiprocessor -Systems-on-Chip together with their basic operating system on the other end. -\parlf -Currently, the lab employs 124 persons among which 60 PhD candidates, and runs -32 ongoing French/European funded projects. -Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions -and had 243 PhD thesis defended. -\parlf -The System Level Synthesis Group (25 people including PhDs) is -involved in several FP6, FP7, CATRENE and ANR projects. -Its field of expertise is in CAD and architecture for Multiprocessor -SoC and Hardware/Software interface. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\ubs} - -The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, -de la Communication, et de la Connaissance), is a French CNRS laboratory -(UMR 3192) that groups 4 research centers in the west and south -Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de -Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). -The Lab-STICC is composed of three departments: Microwave and equipments (MOM), -Digital communications, Architectures and circuits (CACS) and Knowledge, -information and decision (CID). The Lab-STICC represents a staff of 279 -peoples, including 115 researchers and 113 PhD students. -The scientific production during the last 4 years represents 20 -books, 200 journal publications, 500 conference publications, 22 -patents, 69 PhDs diploma. -\parlf -The UBS/Lab-STICC laboratory is involved in several national research -projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, -A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), -CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE -...). It is also involved in European Project (e.g. ITEA/SPICES, -IST/AETHER ...). These projects are conducted through tight cooperation -with national and international companies and organizations (e.g. France -Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, -BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former -projects are for example the high-level synthesis tool GAUT, the UHLS -syntax and semantics-oriented editor, the DSP power estimation tool -Soft-explorer or the co-design framework Design Trotter. -\parlf -The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), -located in Lorient, is involved in COACH. -The UBS/Lab-STICC is working on the design of complex electronic systems -and circuits, especially but not exclusively focussing on real-time -embedded systems, power and energy consumption optimization, high-level -synthesis and IP design, digital communications, hardware/software -co-design and ESL methodologies. The application targeted by the -UBS/Lab-STICC are mainly from telecommunication and multimedia domains -which enclose signal, image, video, vision, and communication processing. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\upmc} - -University Pierre et Marie Curie (UPMC) is the largest university in France (7400 -employees,38000 students). -The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of -UPMC, hosting more than 400 researchers, under the umbrella of the CNRS (Centre National -de la Recherche Scientifique). -The \og System on Chip \fg Department of LIP6 consists of 80 people, including 40 PHD -students. -The research focuses on CAD tools and methods for VLSI and System on Chip design. -\\ -The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. -The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, -OMI-MACRAME, OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ -TSAR. -\parlf -The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than -200 universities worldwide. -The LIP6 is in charge of the technical coordination of the SoCLib national project, and is -hosting the SoCLib WEB server. -The SoCLib DSX component was designed and developped in our laboratory. -It allows design space exploration and will the base of the $CSG$ COACH tools. -Moreover, the LIP6 developped during the last 10 years the UGH tool for high level -synthesis of control-dominated coprocessors. -This tool will be modified to be integrated in the COACH design flow. -\parlf -Even if the preferred dissemination policy for the COACH design flow will be the free -software policy, the SoC department is ready to support start-ups : -Six startup companies have been created by former -researchers from the SoC department of LIP6 between 1997 and 2002. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\xilinx} - -\xilinx is the world leader in the domain of programmable logic circuits (FPGA). -\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex -families) and on the other hand a software solution allowing exploiting the -characteristics of these FPGA. -\parlf -The tools proposed allow the designer to describe his architecture from a modeling -language (VHDL/Verilog) to an optimized architecture implemented to the selected -technology. -The team located at Grenoble is responsible of the logic synthesis tool development (XST) -of the software solution, which aggregates all the steps allowing proceeding from a HDL -model to a technological netlist: -\begin{itemize} - \item Compilation of HDL code and model generation at Register Transfer Level (RTL). - \item RTL model optimizations. - \item Inference and generation of optimized macro blocks (Finite states machine, counter). - \item Boolean equations generation for random logic. - \item Logical, mapping and timing optimizations. -\end{itemize} -\parlf -The architectures developed by \xilinx offer a collection of technological primitives -(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory -and even configurable processor cores (Pico and MicroBlaze families). -This kind of architecture allows, therefore, the designer to validate different -hardware/software possibilities in a High Level Synthesis (HLS) framework. -\parlf -The classical optimization techniques focus, mainly, on the frequency aspects and on -available resources use. -The optimizations, taking into account the consumption criteria, become critical due to -the fact of the increase of the architecture complexity and due to the use of FPGA -component for low power applications. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\mds} - -\mustbecompleted{A COMPLETER: Emmanuel ....} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\bull} - -\bull designs and develops servers and software for an open environment, integrating the -most advanced technologies. It brings to its customers its expertise and know-how to help -them in the transformation of their information systems and to optimize their IT -infrastructure and their applications. -\parlf -\bull is particularly present in the public sector, banking, finance, telecommunication -and industry sectors. Capitalizing on its wide experience, the Group has a thorough -understanding of the business and specific processes of these sectors, thus enabling it to -efficiently advise and to accompany its customers. Its distribution network spreads to -over 100 countries worldwide. -\parlf -The team participating to the COACH project is from the Server Development Department -based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing -hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range -from architecture specification, ASIC design/verification/prototyping to board design and -include also specific EDA development to complement standard tools. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\thales} - -\thales is a world leader for mission critical information systems, with activities in 3 -core businesses: aerospace (with all major aircraft manufacturers as customers), defence, -and security (including ground transportation solutions). It employs 68000 people -worldwide, and is present in 50 countries. \thales Research \& Technology operates at the -corporate level as the technical community network architect, in charge of developing -upstream and \thales-wide R \& T activities, with vision and visibility. In support of -\thales applications, TRT's mission is also to anticipate and speed up technology transfer -from research to development in Divisions by developing collaborations in R\&T. \thales is -international, but Europe-centered. Research \& Development activities are disseminated, -and corporate Research and Technology is concentrated in Centres in France, the United -Kingdom and the Netherlands. A key mission of our R\&T centres is to have a bi-directional -transfer, or "impedance matching" function between the scientific research network and the -corresponding businesses. The TRT's Information Science and Technology Group is able to -develop innovative solutions along the information chain exploiting sensors data, through -expertise in: computational architectures in embedded systems, typically suitable for -autonomous system environments, mathematics and technologies for decision involving -information fusion and cognitive processing, and cooperative technologies including man -system interaction. -\parlf -The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the -Information Science and Technology Group. Like other labs of TRT, ESL is in charge of -making the link between the needs from \thales business units and the emerging -technologies, in particular through assessment and de-risking studies. It has a long -experience on parallel architectures design, in particular on SIMD architectures used for -image processing and signal processing applications and on reconfigurable architectures. -ESL is also strongly involved in studies on programming tools for these types of -architectures and has developed the SpearDE tool used in this project. The laboratory had -coordinated the FP6 IST MORPHEUS project on reconfigurable technology, being highly -involved in the associated programming toolset. The team is also involved in the FP6 IST -FET AETHER project on self-adaptability technologies and coordinates national projects on -MPSoC architecture and tools like the Ter\verb+@+ops project (P\^{o}le de -Comp\'{e}titivit\'{e} System\verb+@+tic) dedicated to the design of a MPSoC for intensive -computing embedded systems. - Index: r/section-6.2.tex =================================================================== --- /anr/section-6.2.tex (revision 288) +++ (revision ) @@ -1,32 +1,0 @@ -The Coach project will be coordinated by the Professor Alain Greiner from -Université Pierre et Marie Curie. -Alain Greiner is the initiator and the main architect of the SoCLib project. -This ANR plat-form for virtual prototyping of MPSoCs involved 6 industrial companies -(including ST Microelectronics and Thales) and ten academic laboratories -(5 of them are involved in the Coach project). -The SoCLib project was managed by Thales, but the technical coordination has been done -by Alain Greiner, that has a good experience in coordinating large technical projects -in both industrial and academic contexts: - -\begin {itemize} -\item -He received the "Docteur es Sciences" degree from University Denis DIDEROT -in 1982 after working six years at Commissariat a l' Energie Atomique. -\item -From 1986 to 1990, he worked for the french BULL company, as team leader, -in charge of designing the Basic Processing Unit for the BULL -DPS7000 computer, the most powerfull mainframe from the family. -\item -In 1990, Alain Greiner joined UPMC, as Professor and became the head of the -MASI laboratory in 1994. -\item -From 1990 to 2000, he was the leader of the the ALLIANCE project: This GPL based -cooperative project developped a public domain VLSI/CAD system that has been used -in more than 200 universities worlwide, for education and research. -This project obtained the Seymour Cray award in 1994. -\item -From 2000 to 2009, he was the head of the Hardware Department -of the LIP6 laboratory, and associate-director of the LIP6 laboratory. -\end {itemize} - - Index: r/section-7.tex =================================================================== --- /anr/section-7.tex (revision 288) +++ (revision ) @@ -1,268 +1,0 @@ -\def\resstablestyletitle#1{\begin{small}{\textit{#1}}\end{small}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 1: \irisa} - -\begin{description} -\item [Equipment] - No specific equipment acquisition. -\item [Personnel costs] The faculty members involved in the project - are François Charot (INRIA researcher), Steven Derrien (associate - professor), Christophe Wolinski (professor) and Charles Wagner - (research engineer). The non-permanent personal required is a PhD - student that will mainly work on ASIP generation. We are looking for - a profile with strong informatic skills and good knowledge in - computer architecture. - \parlf - The table below summarizes the manpower in \hommemois by tasks for both permanent and - non-permanent personnels. The detail by deliverables is given in - figure~\ref{table-livrables-1}. - The non-permanent personnels costs represent {48\%} of the personnal - costs. The requested funding for non permanent personnels is 100\% of - the total ANR requested funding. - \begin{center}\input{table_inria_cairn_short.tex}\end{center} -\item [Subcontracting] - No subcontracting costs. -\item [Travel] - The travel costs are associated to project meeting as well as participation to - conferences. The travel costs are estimated to {7,5\%} of the total - requested ANR funding. -\item [Expenses for inward billing] - The costs justified by internal invoicing procedures are evaluated to 4\% of the total - requested ANR funding. -\end{description} - - -\subsection{Partner 2: \lip} - -\begin{description} -\item [Equipment] - No specific equipment acquisition. The costs for depreciation of - workstations is evaluated to 4\% of the total requested ANR funding. -\item [Personnel costs] - The faculty members involved in the project are an emeritus - professor at ENS Lyon (Paul Feautrier) and a research associate - (CR2) at INRIA Rh\^one-Alpes (Christophe Alias). The non-permanent - personel required is a PhD student that will work on network process - generation from polyhedral loops, then on extensions to - non-polyhedral loops. We are looking for a student with both - theoretical and practical skills, that will be able to get a - sufficient understanding of the polyhedral techniques and to produce - a working implementation. - \parlf - The table below summarizes the \hommemois by - deliverables and tasks for both permanent and non-permanent - personnels. The non-permanent personnels costs represent 26\% of - the personnal costs. The requested funding for non - permanent personnels is 100\% of the total ANR requested funding. - \begin{center}\input{table_inria_compsys_full.tex}\end{center} -\item [Subcontracting] - No subcontracting costs. -\item [Travel] - The travel costs are associated to project meeting as well as - participation to conferences. The travel costs are estimated to 20\% - of the total requested ANR funding. -\item [Expenses for inward billing] - The costs justified by internal invoicing procedures are evaluated - to 4\% of the total requested ANR funding. -\end{description} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 3: \tima} - -\begin{description} -\item [Equipment] - No specific equipment acquisition. -\item [Personnel costs] - The permanent personnels involved in the project are professor and assistant professor - (Fr\'ed\'eric P\'etrot and Olivier Muller). - The non permanent personnels are Phd students and post-doc researchers. - Related costs are estimated in \hommemois. - One phd student (Adrien Prost-Boucle), funded by the french ministry of research, will - be working on the project. - One 100\% funded phd student will be hired in september 2010. A post-doc researcher will - be hired at the end of 2011 for one year and an half. - The PhD student will mainly work on the evolution of UGH HLS tool. Thus, we are looking - for a profile with strong informatic skills and good knowledge in computer architecture. - The post-doc will mainly work on dynamic reconfiguration and HPC. The required profile - will be more oriented on computer architecture and advanced digital design. - \parlf - The table below sumarizes the man power in \hommemois by tasks for both permanent and - non-permanent personnels. The detail by deliverables is given in - figure~\ref{table-livrables-1}. - The requested funding for personnels represent 50\% of the total personnal costs. - The requested funding for non permanent personnels is 85\% of the total ANR requested - funding. - \begin{center}\input{table_tima_short.tex}\end{center} -\item [Subcontracting] - No subcontracting costs. -\item [Travel] - The travel costs are associated to project meeting as well as participation to - conferences. The travel costs are estimated to 11\% of the total requested ANR funding. -\item [Expenses for inward billing] - The costs justified by internal invoicing procedures are evaluated to 4\% of the total - requested ANR funding. -\end{description} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 4: \ubs} - -\begin {description} -\item [Equipment] - In order to validate the design flow project, the Lab-STICC laboratory will buy FPGA - developpement boards. The cost for these FPGA boards is estimated to 3\% of the total - ANR funding. -\item [Personnel costs] - The faculty members involved in the project are associate professors (Philippe COUSSY, - Cyrille CHAVET) or research engineers (Dominique HELLER). All non-permanent personnel - costs are estimated in \hommemois for senior researchers (post-doc or research - engineers). - \parlf - The table below sumarizes the man power in \hommemois by tasks for both permanent and - non-permanent personnels. The detail by deliverables is given in - figure~\ref{table-livrables-2}. - The non-permanent personnels costs represent 50\% of the personnal costs. - The requested funding for non permanent personnels is about 83\% of the total ANR - requested funding. - \begin{center}\input{table_ubs_short.tex}\end{center} -\item [Subcontracting] - No subcontracting costs. -\item [Travel] - The travel costs are associated to management and meeting as well as participation to - conferences. The travel costs are estimated to 10\% of the total requested ANR funding. -\item [Expenses for inward billing] - The costs justified by internal invoicing procedures are evaluated to 4\% of the total - requested ANR funding. -\end {description} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 5: \upmc} - -\begin{description} -\item[Equipment] - No specific equipment acquisition is required for this project. - The costs for depreciation of workstations and pre-existing FPGA boards are evaluated - to 7\% of the total requested ANR funding. -\item[Personnel costs] - The permanent personnels involved in the project are professors or assistant - processors (Alain Greiner and Ivan Aug\'e). - All non permanent personnel costs are estimated in \hommemois for senior researchers - (post-doc or research engineers). - The table below sumarizes the man power by tasks in \hommemois for both permanent and - non-permanent personnels. - The detail by deliverables is given in figure~\ref{table-livrables-2}. - The non-permanent personnels costs represent 50\% of the personnal costs. - The requested funding for non permanent personnels is 79\% of the total ANR - requested funding. - \begin{center}\input{table_upmc_short.tex}\end{center} -\item[Subcontracting] - No subcontracting costs. -\item[Travel] - The travel costs are associated to management and coordination meeting as - well as participation to conferences. The travel costs are estimated - to 10\% of the total requested ANR funding. -\item[Expenses for inward billing] - The costs justified by internal invoicing procedures are evaluated to 4\% - of the total requested ANR funding. -\end{description} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 6: \mds} - -\mustbecompleted{A COMPLETER: Emmanuel ....} -\begin{ADDEDENV} -\begin{description} -\item[Equipment] - No specific equipment acquisition is required for this project. -\item[Personnel costs] - \xilinx employees involved in the project are permanent Software Engineers. - The man power detail in \hommemois by deliverables is given in - figure~\ref{table-livrables-1} and a sumary by task in the following table. - \begin{center}\input{table_mds_short.tex}\end{center} -\item[Subcontracting] - No subcontracting costs. -\item[Travel] - The travel costs are associated to project meeting as well as participation to - conferences. The travel costs are estimated to 2\% of the total requested ANR funding. -\item[Expenses for inward billing] none -\item[Other working costs] none -\end{description} -\end{ADDEDENV} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 7: \bull} - -\begin{description} -\item[Equipment] - Acquisition of a FPGA development board will represent the main equipment cost for - Bull in COACH. It is estimated at about 5\% (tbc) of the total funding. -\item[Personnel costs] - A permanent engineer will be assigned full time to the project for a duration of 20 - months as shown in the table below that gives the man power in \hommemois: - \begin{center}\input{table_bull_full.tex}\end{center} -\item[Subcontracting] - No subcontracting costs. -\item[Travel] - Application of a standard 10\% of the total funding to travel costs. -\item[Expenses for inward billing] - Costs justified by inward billing are estimated to about 5\% of the total funding. -\item[Other working costs] none -\end{description} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 8: \thales} - -\begin{description} -\item[Equipment] - In order to validate the design flow,TRT will buy FPGA developpement boards. The cost - for these FPGA boards is estimated to 10 k\euro (6\% of the total ANR funding). -\item[Personnel costs] - The effort to adapt SPEAR DE to generate the input files to COACH framework is - estimated to 13 \hommemois. - The effort to describe and develop the application is estimated to 14 \hommemois. - Finally we need one \hommemois for the partiticipation to the global specification in task 2. - This is sumarized in the table below: - \begin{center}\input{table_thales_full.tex}\end{center} -\item[Subcontracting] - No subcontracting costs. -\item[Travel] - The travel costs are associated to meeting, plenaries as well as participation to - conferences. The travel costs are estimated to 10 k\euro. The travel costs are estimated to - 5\% of the total requested ANR funding. -\item[Expenses for inward billing] none -\item[Other working costs] none -\end{description} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% -\begin{landscape} -\begin{figure} -\begin{small} -\settowidth\desclen{XILINX RTL optimisation (5)} -\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} -\begin{minipage}[b]{.47\linewidth}\center -\input{table_inria_cairn_full.tex}\vspace{.5ex}\\ \irisa \vspace{2.5ex}\\ -\input{table_mds_full.tex}\vspace{.5ex}\\ \mds \\ -\end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center -\input{table_tima_full.tex}\vspace{.5ex} \\ \tima -\end{minipage} -\end{small} -\caption{\label{table-livrables-1} Man power in \hommemois for the deliverables (1)} -\end{figure} -% -\begin{figure} -\begin{small} -\settowidth\desclen{XILINX RTL optimisation (5)} -\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} -\begin{minipage}[b]{.47\linewidth}\center -\input{table_ubs_full.tex}\vspace{.5ex}\\ \ubs \vspace{2.5ex}\\ -%\input{table_thales_full.tex}\vspace{.5ex}\\ \thales \\ -\end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center -\input{table_upmc_full.tex}\vspace{.5ex} \\ \upmc -\end{minipage} -\end{small} -\caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (2)} -\end{figure} -\end{landscape} Index: /anr/section-consortium-desc.tex =================================================================== --- /anr/section-consortium-desc.tex (revision 289) +++ /anr/section-consortium-desc.tex (revision 289) @@ -0,0 +1,263 @@ +\anrdoc{(maximum 0,5 page par partenaire) Decrire brievement chaque +partenaire et fournir ici les elements permettant d'apprecier la +qualification des partenaires dans le projet (le \og pourquoi qui fait quoi +\fg). Il peut s'agir de realisations passees, d'indicateurs (publications, +brevets), de l'interet du partenaire pour le projet.\\ +Montrer la complementarite et la valeur ajoutee des cooperations entre les +differents partenaires. L'interdisciplinarite et l'ouverture à diverses +collaborations seront à justifier en accord avec les orientations du +projet. (1 page maximum)} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\inria/CAIRN} + +INRIA, the French national institute for research in computer science +and control, operating under the dual authority of the Ministry of +Research and the Ministry of Industry, is dedicated to fundamental and +applied research in information and communication science and +technology (ICST). The Institute also plays a major role in technology +transfer by fostering training through research, diffusion of +scientific and technical information, development, as well as +providing expert advice and participating in international programs. +\parlf +By playing a leading role in the scientific community in the field and +being in close contact with industry, INRIA is a major participant in +the development of ICST in France. Throughout its eight research +centres in Rocquencourt, Rennes, Sophia Antipolis, Grenoble, Nancy, +Bordeaux, Lille and Saclay, INRIA has a workforce of 3 800, 2 800 of +whom are scientists from INRIA and INRIA's partner organizations such +as CNRS (the French National Center for Scientific Research), +universities and leading engineering schools. They work in 168 joint +research project-teams. Many INRIA researchers are also professors and +approximately 1 000 doctoral students work on theses as part of INRIA +research project-teams. +%\parlf +%INRIA develops many partnerships with industry and fosters technology +%transfer and company foundation in the field of ICST - some ninety +%companies have been founded with the support of INRIA-Transfert, a +%subsidiary of INRIA, specialized in guiding, evaluating, qualifying, +%and financing innovative high-tech IT start-up companies. INRIA is +%involved in standardization committees such as the IETF, ISO and the +%W3C of which INRIA was the European host from 1995 to 2002. +%\parlf +%INRIA maintains important international relations and exchanges. In +%Europe, INRIA is a member of ERCIM which brings together research +%institutes from 19 European countries. INRIA is a partner in about 120 +%FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also +%collaborates with numerous scientific and academic institutions abroad +%(joint laboratories such as LIAMA, associated research teams, training +%and internship programs). + +The CAIRN group of INRIA Rennes -- Bretagne Atlantique study reconfigurable +system-on-chip, i.e. hardware systems whose configuration may change before or even during +execution. To this end, CAIRN has 13 permanent researchers and a variable number of PhD +students, post-docs and engineers. +CAIRN intends to approach reconfigurable architectures from three +angles: the invention of new reconfigurable platforms, the development +of associated transformation, compilation and synthesis tools, and the +exploration of the interaction between algorithms and architectures. +CAIRN is a joint team with CNRS, University of Rennes 1 and ENS Cachan. + +\subsubsection{\lip/Compsys} +The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team +of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du +Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers +and a variable number of PhD students and post-docs. Its field of +expertise is compilation for embedded system, optimizing compilers +and automatic parallelization. Its members were among the initiators +of the polyhedral model for automatic parallelization and program +optimization generally. It has authored or contributed to +several well known libraries for linear programming, polyhedra manipulation +and optimization in general. It has strong industrial cooperations, notably +with ST Microelectronics and \thales. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\tima} +The TIMA laboratory ("Techniques of Informatics and Microelectronics +for integrated systems Architecture") is a public research laboratory +sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159), +Grenoble Institute of Technology (Grenoble-INP) and Universit\'{e} Joseph Fourier +(UJF). +The research topics cover the specification, design, verification, test, +CAD tools and design methods for integrated systems, from analog and +digital components on one end of the spectrum, to multiprocessor +Systems-on-Chip together with their basic operating system on the other end. +\parlf +Currently, the lab employs 124 persons among which 60 PhD candidates, and runs +32 ongoing French/European funded projects. +Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions +and had 243 PhD thesis defended. +\parlf +The System Level Synthesis Group (25 people including PhDs) is +involved in several FP6, FP7, CATRENE and ANR projects. +Its field of expertise is in CAD and architecture for Multiprocessor +SoC and Hardware/Software interface. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\ubs} + +The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, +de la Communication, et de la Connaissance), is a French CNRS laboratory +(UMR 3192) that groups 4 research centers in the west and south +Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de +Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). +The Lab-STICC is composed of three departments: Microwave and equipments (MOM), +Digital communications, Architectures and circuits (CACS) and Knowledge, +information and decision (CID). The Lab-STICC represents a staff of 279 +peoples, including 115 researchers and 113 PhD students. +The scientific production during the last 4 years represents 20 +books, 200 journal publications, 500 conference publications, 22 +patents, 69 PhDs diploma. +\parlf +The UBS/Lab-STICC laboratory is involved in several national research +projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, +A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), +CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE +...). It is also involved in European Project (e.g. ITEA/SPICES, +IST/AETHER ...). These projects are conducted through tight cooperation +with national and international companies and organizations (e.g. France +Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, +BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former +projects are for example the high-level synthesis tool GAUT, the UHLS +syntax and semantics-oriented editor, the DSP power estimation tool +Soft-explorer or the co-design framework Design Trotter. +\parlf +The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), +located in Lorient, is involved in COACH. +The UBS/Lab-STICC is working on the design of complex electronic systems +and circuits, especially but not exclusively focussing on real-time +embedded systems, power and energy consumption optimization, high-level +synthesis and IP design, digital communications, hardware/software +co-design and ESL methodologies. The application targeted by the +UBS/Lab-STICC are mainly from telecommunication and multimedia domains +which enclose signal, image, video, vision, and communication processing. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\upmc} + +University Pierre et Marie Curie (UPMC) is the largest university in France (7400 +employees,38000 students). +The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of +UPMC, hosting more than 400 researchers, under the umbrella of the CNRS (Centre National +de la Recherche Scientifique). +The \og System on Chip \fg Department of LIP6 consists of 80 people, including 40 PHD +students. +The research focuses on CAD tools and methods for VLSI and System on Chip design. +\\ +The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. +The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, +OMI-MACRAME, OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ +TSAR. +\parlf +The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than +200 universities worldwide. +The LIP6 is in charge of the technical coordination of the SoCLib national project, and is +hosting the SoCLib WEB server. +The SoCLib DSX component was designed and developped in our laboratory. +It allows design space exploration and will the base of the $CSG$ COACH tools. +Moreover, the LIP6 developped during the last 10 years the UGH tool for high level +synthesis of control-dominated coprocessors. +This tool will be modified to be integrated in the COACH design flow. +\parlf +Even if the preferred dissemination policy for the COACH design flow will be the free +software policy, the SoC department is ready to support start-ups : +Six startup companies have been created by former +researchers from the SoC department of LIP6 between 1997 and 2002. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\xilinx} + +\xilinx is the world leader in the domain of programmable logic circuits (FPGA). +\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex +families) and on the other hand a software solution allowing exploiting the +characteristics of these FPGA. +\parlf +The tools proposed allow the designer to describe his architecture from a modeling +language (VHDL/Verilog) to an optimized architecture implemented to the selected +technology. +The team located at Grenoble is responsible of the logic synthesis tool development (XST) +of the software solution, which aggregates all the steps allowing proceeding from a HDL +model to a technological netlist: +\begin{itemize} + \item Compilation of HDL code and model generation at Register Transfer Level (RTL). + \item RTL model optimizations. + \item Inference and generation of optimized macro blocks (Finite states machine, counter). + \item Boolean equations generation for random logic. + \item Logical, mapping and timing optimizations. +\end{itemize} +\parlf +The architectures developed by \xilinx offer a collection of technological primitives +(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory +and even configurable processor cores (Pico and MicroBlaze families). +This kind of architecture allows, therefore, the designer to validate different +hardware/software possibilities in a High Level Synthesis (HLS) framework. +\parlf +The classical optimization techniques focus, mainly, on the frequency aspects and on +available resources use. +The optimizations, taking into account the consumption criteria, become critical due to +the fact of the increase of the architecture complexity and due to the use of FPGA +component for low power applications. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\mds} + +\mustbecompleted{A COMPLETER: Emmanuel ....} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\bull} + +\bull designs and develops servers and software for an open environment, integrating the +most advanced technologies. It brings to its customers its expertise and know-how to help +them in the transformation of their information systems and to optimize their IT +infrastructure and their applications. +\parlf +\bull is particularly present in the public sector, banking, finance, telecommunication +and industry sectors. Capitalizing on its wide experience, the Group has a thorough +understanding of the business and specific processes of these sectors, thus enabling it to +efficiently advise and to accompany its customers. Its distribution network spreads to +over 100 countries worldwide. +\parlf +The team participating to the COACH project is from the Server Development Department +based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing +hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range +from architecture specification, ASIC design/verification/prototyping to board design and +include also specific EDA development to complement standard tools. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{\thales} + +\thales is a world leader for mission critical information systems, with activities in 3 +core businesses: aerospace (with all major aircraft manufacturers as customers), defence, +and security (including ground transportation solutions). It employs 68000 people +worldwide, and is present in 50 countries. \thales Research \& Technology operates at the +corporate level as the technical community network architect, in charge of developing +upstream and \thales-wide R \& T activities, with vision and visibility. In support of +\thales applications, TRT's mission is also to anticipate and speed up technology transfer +from research to development in Divisions by developing collaborations in R\&T. \thales is +international, but Europe-centered. Research \& Development activities are disseminated, +and corporate Research and Technology is concentrated in Centres in France, the United +Kingdom and the Netherlands. A key mission of our R\&T centres is to have a bi-directional +transfer, or "impedance matching" function between the scientific research network and the +corresponding businesses. The TRT's Information Science and Technology Group is able to +develop innovative solutions along the information chain exploiting sensors data, through +expertise in: computational architectures in embedded systems, typically suitable for +autonomous system environments, mathematics and technologies for decision involving +information fusion and cognitive processing, and cooperative technologies including man +system interaction. +\parlf +The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the +Information Science and Technology Group. Like other labs of TRT, ESL is in charge of +making the link between the needs from \thales business units and the emerging +technologies, in particular through assessment and de-risking studies. It has a long +experience on parallel architectures design, in particular on SIMD architectures used for +image processing and signal processing applications and on reconfigurable architectures. +ESL is also strongly involved in studies on programming tools for these types of +architectures and has developed the SpearDE tool used in this project. The laboratory had +coordinated the FP6 IST MORPHEUS project on reconfigurable technology, being highly +involved in the associated programming toolset. The team is also involved in the FP6 IST +FET AETHER project on self-adaptability technologies and coordinates national projects on +MPSoC architecture and tools like the Ter\verb+@+ops project (P\^{o}le de +Comp\'{e}titivit\'{e} System\verb+@+tic) dedicated to the design of a MPSoC for intensive +computing embedded systems. + Index: /anr/section-consortium-leader.tex =================================================================== --- /anr/section-consortium-leader.tex (revision 289) +++ /anr/section-consortium-leader.tex (revision 289) @@ -0,0 +1,5 @@ +\anrdoc{(0,5 page maximum)\\ +Fournir les elements permettant de juger la capacite du coordinateur à +coordonner le projet.} + +\mustbecompleted{EMANNUEL} Index: /anr/section-consortium-people.tex =================================================================== --- /anr/section-consortium-people.tex (revision 289) +++ /anr/section-consortium-people.tex (revision 289) @@ -0,0 +1,24 @@ +\anrdoc{(2 pages maximum)\\ +Qualifier les personnes, preciser leurs activites principales et leurs competences propres. +Pour chaque partenaire remplir le tableau ci-dessous.\\ +Pour chacune des personnes dont l'implication dans le projet est superieure a +25\% de son temps sur la totalite du projet (c'est-a-dire une moyenne de 3 +hommes.mois par annee de projet), une biographie d'une page maximum sera placee +en annexe 7.2 du present document qui comportera: +\begin{itemize} +\item Nom, prenom, age, cursus, situation actuelle +\item Autres experiences professionnelles +\item Liste des cinq publications (ou brevets) les plus significatives des + cinq dernieres annees, nombre de publications dans les revues + internationales ou actes de congres a comite de lecture. +\item Prix, distinctions +\end{itemize} +Si besoin, pour chacune des personnes, leur implication dans d'autres projets +(Contrats publics et prives effectues ou en cours sur les trois dernieres +annees) sera presentee selon le modele fourni en annexe. Les tableaux seront +places en annexe 7.3. On precisera l'implication dans des projets europeens ou +dans d'autres types de projets nationaux ou internationaux. Expliciter +l'articulation entre les travaux proposes et les travaux anterieurs ou deja en +cours.} + + Index: /anr/section-dissemination.tex =================================================================== --- /anr/section-dissemination.tex (revision 289) +++ /anr/section-dissemination.tex (revision 289) @@ -0,0 +1,161 @@ +\anrdoc{A titre indicatif: 2 pages pour ce chapitre.\\ +Presenter les strategies de valorisation des resultats: +\begin{itemize} +\item la communication scientifique; +\item la communication aupres du grand public (un budget specifique peut être prevu), +\item la valorisation des resultats attendus, +\item les retombees scientifiques, techniques, industrielles, economiques, ... +\item la place du projet dans la strategie industrielle des entreprises partenaires du projet +\item autres retombees (normalisation, information des pouvoirs publics, ...) +\item les echeances et la nature des retombees technico- economiques attendues +\item l'incidence eventuelle sur l'emploi, la creation d'activites nouvelles. +\end{itemize} +Presenter les grandes lignes des modes de protection et d'exploitation des resultats\\ +Pour les projets partenariaux organismes de recherche/entreprises, les +partenaires devront conclure, sous l'egide du coordinateur du projet, un +accord de consortium dans un delai de un an si le projet est retenu pour +financement.\\ +Pour les projets academiques, l'accord de consortium n'est pas obligatoire +mais fortement conseille.} + +\subsection{Dissemination} + +The COACH project will bring new scientific results in various fields, such as high level synthesis, +hardware/software codesign, virtual prototyping, hardware oriented compilation techniques, +automatic parallelisation, etc. These results will be published in relevant International +Conferences, namely DATE, DAC, or ICCAD. + +More generally, the COACH infrastructure and the design flow supported by the COACH +tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis +in various worshops and conferences (DATE, DAC, CODES+ISSS...). + +Several COACH partners being members of the HiPEAC European Network of Excellence +(High Performance and Embedded Architecture and Compilation), courses will be proposed for the +HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems. + +Following the general policy of the SoCLib platform, the COACH project will be an +open infrastructure, and the COACH tools and libraries will be available in the framework +of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. + +\subsection{Exploitation of results} + +The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) +to enter the world of MPSoC technologies. For small companies, the cost is a primary concern. +Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling. +As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus +on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) +tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform : + +\begin{itemize} +\item +All software tools supporting the COACH design flow will be available as free software. +All academic partners contributing to the COACH project agreed to distribute the ESL software +tools under the same GPL license as the SoCLib tools. +\item +The SystemC simulation models for the hardware components +used by the SoCLib architectural template will be distributed as free software +under a non-contaminant LGPL license. +\item +The synthesizable VHDL models supporting the neutral architectural template +(corresponding to the SocLib IP cores library), will have two modes of dissemination. +A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains +also general purpose, reusable components, such as processor cores, memory controllers +optimised cache controllers, peripheral controllers, or bus controllers. +For non commercial use (i.e. research or education in an academic context, +or feasibility study in an industrial context), the synthesizable VHDL models will be freely available. +For commercial use, commercial licenses will be negotiated between the owners and the customers. +\item +The proprietary \altera and \xilinx IP core libraries are commercial products +that are not involved by the free software policy, but these libraries will be supported by the +synthesis tools developed in the COACH project. +\end{itemize} + +This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as +demonstrated by the "letters of interest" that have been collected during the preparation +of the project and presented in annexe~\ref{lettre-soutien}. + +\subsection{Indusrial Interest in COACH} + +\subsubsection*{Partner: \textit{\mds}} + +\mustbecompleted{A COMPLETER: Emmanuel ....} + +\subsubsection*{Partner: \textit{\bull}} +The team of \bull participating to the COACH project is from the Server Development +Department who is in charge of developing hardware for open servers (e.g. NovaScale) and +HPC solutions. The main expectation from COACH is to derive a new component (fine-grain +FPGA parallelism) to add to existing Bull HPC solutions. + +%\subsubsection*{Partner: \textit{\xilinx}} +%Computing power potential of our FPGA architectures +%growing very quickly on one side, and complexity of designs implemented +%using our FPGAs dramatically increasing on the other side, it is very +%interesting for us to get high level design methodologies progressing +%quickly and targetting our FPGAs in the most possible efficient way. +%\parlf +%\xilinx goal is to get COACH to generate bitstream optimized as much as possible for +%\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease +%future work of our customers. + +\subsubsection*{Partner: \textit{\thales}} +\noindent +\thales has two main reasons to use the COACH platform: +\begin{itemize} + \item The huge increase of the complexity of the systems in particular by their + heterogeneity, raises the issues of design cost and time in the same proportion. The + divisions need a design tool which supports the implementation of the applications from + algorithm description to the executable code on platforms composed of several general + purpose processors and dedicated IPs. + \item The applications are more and more complex and adaptable to the environment which + leads to a mixture of control aspects and data stream computing aspects. A new approach + is necessary to be able to describe this type of application and manage the high level + synthesis of system embedding control and data flow aspects. +\end{itemize} +\parlf +TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging +technologies in its domains of expertise. Specifically in COACH, the studied technology is +a method and associated tools to make the bridge between application capture at system +level and the implementation on heterogeneous distributed computing architectures. The +main stake for Thales behind this is the future design process that will be applied to its +system teams in the future for the computation-intensive sensor applications. In a context +of very instable market of tools for parallel programming, it is important to experiment +and demonstrate the candidate technologies. +\\ +In its role of internal dissemination, TRT will make the demonstration of the full design +flow within Thales, and will keep available a platform to later evaluate additional +applications coming from the Business Units. +\\ +The COACH platform will be used in the new \thales products in which the algorithms are more +and more dependent of the environment and have to permanently adapt their behavior in +varying environments. The target markets are the critical infrastructures security and +border monitoring. + +\subsubsection*{Industrial supports} + +\mustbecompleted{NON A JOUR} +The following SMEs demonstrate interest to the COACH project (see the "letters of +interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will +evaluate it: +\letterOfInterest{ALTERA Corporation}{lettres/Altera1.pdf}, +\letterOfInterestPlus{lettres/Altera2.pdf} +\letterOfInterest{ADACSYS}{lettres/Coach_ADACSYS_lettre_interet}, +\letterOfInterest{MAGILLEM Design Services}{lettres/Coach_lettre_interet_MDS}, +\letterOfInterest{INPIXAL}{lettres/inpixal.jpg}, +\letterOfInterest{CAMKA System}{lettres/CAMKA-System.pdf}, +\letterOfInterest{ATEME}{lettres/ATEME.pdf}, +\letterOfInterest{ALSIM Simulateur}{lettres/Alsim.pdf}, +\letterOfInterest{SILICOMP-AQL}{lettres/itlabs.pdf}, +\letterOfInterest{ABOUND Logic}{lettres/abound.pdf}, +\letterOfInterest{EADS-ASTRIUM}{lettres/Astrium1.pdf}. +\letterOfInterestPlus{lettres/Astrium2.pdf} + +\letterOfInterestClose + +\subsection{Management of Intellectual Property} +A global consortium agreement will be defined during the first six monts of the project. +As already stated, the COACH project has been prepared during one year by a monthly meeting +involving the five academic partners. The general free software policy described in the +previous section has been agreed by academic partners and has been +approved by all industrial participants. This free software policy will +simplify the definition of the consortium agreement. + Index: /anr/section-etat-de-art.tex =================================================================== --- /anr/section-etat-de-art.tex (revision 289) +++ /anr/section-etat-de-art.tex (revision 289) @@ -0,0 +1,238 @@ +% vim:set spell: +% vim:spell spelllang=en: +\anrdoc{\begin{itemize} +\item Presenter un etat de l’art national et international, en dressant l’etat des + connaissances sur le sujet. +\item Faire apparaître d’eventuelles contributions des partenaires de la proposition + de projet a cet etat de l’art. +\item Faire apparaître d’eventuels resultats preliminaires. +\item Inclure les references bibliographiques necessaires en annexe 7.1. +\end{itemize}} + +Our project covers several critical domains in system design in order +to achieve high performance computing. Starting from a high level description we aim +at generating automatically both hardware and software components of the system. + +\subsubsection{High Performance Computing} +% Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language +The High-Performance Computing (HPC) world is composed of three main families of architectures: +many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA. +The first two families are dominating the market by taking benefit +of the strength and influence of mass-market leaders (Intel, Nvidia). +%such as Intel for many-core CPU and Nvidia for GPGPU. +In this market, FPGA architectures are emerging and very promising. +By adapting architecture to the software, % (the opposite is done in the others families) +FPGAs architectures enable better performance +(typically between x10 and x100 accelerations) +while using smaller size and less energy (and heat). +However, using FPGAs presents significant challenges~\cite{hpc06a}. +First, the operating frequency of an FPGA is low compared to a high-end microprocessor. +Second, based on Amdahl law, HPC/FPGA application performance is unusually sensitive +to the implementation quality~\cite{hpc06b}. +% Thus, the performance strongly relies on the detected parallelism. +% (pour résumer les 2 derniers points) +Finally, efficient design methodology are required in order to +hide FPGA complexity and the underlying implantation subtleties to HPC users, +so that they do not have to change their habits and can have equivalent design productivity +than in others families~\cite{hpc07a}. + +%état de l'art FPGA +HPC/FPGA hardware is only now emerging and in early commercial stages, +but these techniques have not yet caught up. +Industrial (Mitrionics~\cite{hpc08}, Gidel~\cite{hpc09}, Convey Computer~\cite{hpc10}) and academic (CHREC) +researches on HPC-FPGA are mainly conducted in the USA. +None of the approaches developed in these researches are fulfilling entirely the +challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator, +but extension generation is not automated and requires hardware design skills. +Mitrionics has an elegant solution based on a compute engine specifically +developed for high-performance execution in FPGAs. Unfortunately, the design flow +is based on a new programming language (mitrionC) implying important designer efforts and poor portability. +% tool relying on operator libraries (XtremeData), +% Parle t-on de l'OPenFPGA consortium, dont le but est : "to accelerate the incorporation of reconfigurable computing technology in high-performance and enterprise applications" ? + +Thus, much effort is required to develop design tools that translate high level +language programs to FPGA configurations. +Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12} +(DPR, which enables changing a part of the FPGA, while the rest is still working) +appears very interesting for improving HPC performance as well as reducing required area. + +\subsubsection{System Synthesis} +Today, several solutions for system design are proposed and commercialized. +The existing commercial or free tools do not +cover the whole system synthesis process in a full automatic way. Moreover, +they are bound to a particular device family and to IPs library. +The most commonly used are provided by \altera and \xilinx to promote their +FPGA devices. These representative tools used to synthesize SoC on FPGA +are introduced below. +\\ +The \xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a +plug-in to Simulink that enables designers to develop high-performance DSP +systems for \xilinx FPGAs. +Designers can design and simulate a system using MATLAB and Simulink. The +tool will then automatically generate synthesizable Hardware Description +Language (HDL) code mapped to \xilinx pre-optimized algorithms. +However, this tool targets only DSP based algorithms, \xilinx FPGAs and +cannot handle a complete SoC. Thus, it is not really a system synthesis tool. +\\ +In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx +Platform Studio XPS from \xilinx allows to describe a system, to synthesis it, +to program it into a target FPGA and to upload a software application. +Both SOPC Builder and XPS, allow designers to select and parameterize components from +an extensive drop-down list of IP cores (I/O core, DSP, processor, bus core, ...) +as well as incorporate their own IP. Nevertheless, all the previously introduced tools +do not provide any facilities to synthesize coprocessors and to simulate the platform +at a high level (SystemC). +System designer must provide the synthesizable description of its own IP-cores with +the feasible bus interface. Design Space Exploration is thus limited +and SystemC simulation is not possible neither at transactional nor at cycle +accurate level. +\\ +In addition, \xilinx System Generator, XPS and SOPC Builder are closed world +since each one imposes their own IPs which are not interchangeable. +Designers can then only generate a synthesized netlist, VHDL/Verilog simulation test +bench and custom software library that reflect the hardware configuration. + +Consequently, a designer developing an embedded system needs to master four different +design environments: +\begin{enumerate} + \item a virtual prototyping environment (in SystemC) for system level exploration, + \item an architecture compiler to define the hardware architecture (Verilog/VHDL), + \item one or several third-party HLS tools for coprocessor synthesis (C to RTL), + \item and finally back-end synthesis tools for the bit-stream generation (RTL to bitstream). +\end{enumerate} +Furthermore, mixing these tools requires an important interfacing effort and this makes +the design process very complex and achievable only by designers skilled in many domains. + +\subsubsection{High Level Synthesis} +High Level Synthesis translates a sequential algorithmic description and a +set of constraints (area, power, frequency, ...) to a micro-architecture at +Register Transfer Level (RTL). +Several academic and commercial tools are today available. The most common +tools are SPARK~\cite{spark04}, GAUT~\cite{gaut08}, UGH~\cite{ugh08} in the +academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and +CYNTHETIZER~\cite{cynthetizer} in the commercial world. Despite their +maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}: +\begin{itemize} +\item HLS tools are not integrated into an architecture and system exploration tool. +Thus, a designer who needs to accelerate a software part of the system, must adapt it manually +to the HLS input dialect and perform engineering work to exploit the synthesis result +at the system level, +\item Current HLS tools can not target control AND data oriented applications, +\item HLS tools take into account mainly a unique constraint while realistic design +is multi-constrained. +Low power consumption constraint which is mandatory for embedded systems is not yet +well handled or not handled at all by the HLS tools already available, +\item The parallelism is extracted from initial specification. +To get more parallelism or to reduce the amount of required memory in the SoC, the user +must re-write the algorithmic specification while there is techniques such as polyedric +transformations to increase the intrinsic parallelism, +\item While they support limited loop transformations like loop unrolling and loop +pipelining, current HLS tools do not provide support for design space exploration neither +through automatic loop transformations nor through memory mapping, +\item Despite having the same input language (C/C++), they are sensitive to the style in +which the algorithm dis written. Consequently, engineering work is required to swap from +a tool to another, +\item They do not respect accurately the frequency constraint when they target an FPGA device. +Their error is about 10 percent. This is annoying when the generated component is integrated +in a SoC since it will slow down the whole system. +\end{itemize} +Regarding these limitations, it is necessary to create a new tool generation reducing the gap +between the specification of an heterogeneous system and its hardware implementation \cite{HLSBOOK} \cite{IEEEDT}. + +\subsubsection{Application Specific Instruction Processors} + +ASIP (Application-Specific Instruction-Set Processor) are programmable +processors in which both the instruction and the micro architecture have +been tailored to a given application domain or to a +specific application. This specialization usually offers a good compromise +between performance (w.r.t a pure software implementation on an embedded +CPU) and flexibility (w.r.t an application specific hardware co-processor). +In spite of their obvious advantages, using/designing ASIPs remains a +difficult task, since it involves designing both a micro-architecture and a +compiler for this architecture. Besides, to our knowledge, there is still +no available open-source design flow for ASIP design even if such a tool + would be valuable in the +context of a System Level design exploration tool. +\par +In this context, ASIP design based on Instruction Set Extensions (ISEs) has +received a lot of interest~\cite{NIOS2}, as it makes micro architecture synthesis +more tractable \footnote{ISEs rely on a template micro-architecture in which +only a small fraction of the architecture has to be specialized}, and help ASIP +designers to focus on compilers, for which there are still many open +problems\cite{ARC08}. +This approach however has a severe weakness, since it also significantly reduces +opportunities for achieving good speedups (most speedups remain between 1.5x and +2.5x), since ISEs performance is generally tied down by I/O constraints as +they generally rely on the main CPU register file to access data. + +% ( +%automaticcaly extraction ISE candidates for application code \cite{CODES04}, +%performing efficient instruction selection and/or storage resource (register) +%allocation \cite{FPGA08}). +To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of +micro-architectural ISE models in which the coupling between the processor micro-architecture +and the ISE component is tightened up so as to allow the ISE to overcome the register +I/O limitations. However these approaches generally tackle the problem from a compiler/simulation +point of view and do not address the problem of generating synthesizable representations for +these models. + +We therefore strongly believe that there is a need for an open-framework which +would allow researchers and system designers to : +\begin{itemize} +\item Explore the various level of interactions between the original CPU micro-architecture +and its extension (for example through a Domain Specific Language targeted at micro-architecture +specification and synthesis). +\item Retarget the compiler instruction-selection pass +(or prototype new passes) so as to be able to take advantage of this ISEs. +\item Provide a complete System-level Integration for using ASIP as SoC building blocks +(integration with application specific blocks, MPSoc, etc.) +\end{itemize} + +\subsubsection{Automatic Parallelization} + +The problem of compiling sequential programs for parallel computers +has been studied since the advent of the first parallel architectures +in the 1970s. The basic approach consists in applying program transformations +which exhibit or increase the potential parallelism, while guaranteeing +the preservation of the program semantics. Most of these transformations +just reorder the operations of the program; some of them modify its +data structures. Dependences (exact or conservative) are checked to guarantee +the legality of the transformation. + +This has lead to the invention of many loop transformations (loop fusion, +loop splitting, loop skewing, loop interchange, loop unrolling, ...) +which interact in a complicated way. More recently, it has been noticed +that all of these are just changes of basis in the iteration domain of +the program. This has lead to the introduction of the polyhedral model +\cite{FP:96,DRV:2000}, in which the combination of two transformations is +simply a matrix product. + +Since hardware is inherently parallel, finding parallelism in sequential +programs in an important prerequisite for HLS. The large FPGA chips of +today can accomodate much more parallelism than is available in basic blocks. +The polyhedral model is the ideal tool for finding more parallelism in +loops. + +As a side effect, it has been observed that the polyhedral model is a useful +tool for many other optimization, like memory reduction and locality +improvement. Another point is +that the polyhedral domain \emph{stricto sensu} applies only to +very regular programs. Its extension to more general programs is +an active research subject. + +%\subsubsection{High Performance Computing} +%Accelerating high-performance computing (HPC) applications with field-programmable +%gate arrays (FPGAs) can potentially improve performance. +%However, using FPGAs presents significant challenges~\cite{hpc06a}. +%First, the operating frequency of an FPGA is low compared to a high-end microprocessor. +%Second, based on Amdahl law, HPC/FPGA application performance is unusually sensitive +%to the implementation quality~\cite{hpc06b}. +%Finally, High-performance computing programmers are a highly sophisticated but scarce +%resource. Such programmers are expected to readily use new technology but lack the time +%to learn a completely new skill such as logic design~\cite{hpc07a} . +%\\ +%HPC/FPGA hardware is only now emerging and in early commercial stages, +%but these techniques have not yet caught up. +%Thus, much effort is required to develop design tools that translate high level +%language programs to FPGA configurations. + Index: /anr/section-issues.tex =================================================================== --- /anr/section-issues.tex (revision 289) +++ /anr/section-issues.tex (revision 289) @@ -0,0 +1,138 @@ +\anrdoc{Décrire le contexte économique, social, réglementaire
 dans lequel se +situe le projet en présentant une analyse des enjeux sociaux, économiques, +environnementaux, industriels
 Donner si possible des arguments chiffrés, par +exemple, pertinence et portée du projet par rapport à la demande économique +(analyse du marché, analyse des tendances), analyse de la concurrence, +indicateurs de réduction de coûts, perspectives de marchés (champs +d’application, 
). Indicateurs des gains environnementaux, cycle de vie.} + + +\begin{table}\leavevmode\center +\begin{small}\begin{tabular}{|l|l|l|l|}\hline +Segment & 2010 & 2011 & 2012 \\\hline\hline +Communications & 1,867 & 1,946 & 2,096 \\ +High end & 467 & 511 & 550 \\\hline +Consumer & 550 & 592 & 672 \\ +High end & 53 & 62 & 75 \\\hline +Automotive & 243 & 286 & 358 \\ +High end & - & - & - \\\hline +Industrial & 1,102 & 1,228 & 1,406 \\ +High end & 177 & 188 & 207 \\\hline +Military/Aereo & 566 & 636 & 717 \\ +High end & 56 & 65 & 82 \\\hline\hline +Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ +Total High-End FPGA & 753 & 826 & 914 \\\hline +\end{tabular}\end{small} +\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} +\end{table} +% +Microelectronic components allow the integration of complex functions into products, increases +commercial attractivity of these products and improves their competitivity. +Multimedia and tele-communication sectors have taken advantage from microelectronics facilities +thanks to the developpment of design methodologies and tools for embedded systems. +Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design +and manufacturing ASICs is very high. +An IC foundry costs several billions of euros and the fabrication of a specific circuit +costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 +million USD. +Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium +volume markets. +\parlf +Today, FPGAs become important actors in the computational domain that was originally dominated +by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed +on a per-application basis. For many applications, FPGAs offer significant performance benefits over +microprocessors implementation. There is still a performance degradation of one order +of magnitude versus an equivalent ASIC implementations, but low cost +(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive +choice for low-to-medium volume applications. +Since their introduction in the mid eighties, FPGAs evolved from a simple, +low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that +provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, +on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement +complex systems like multi-processors platform with application dedicated coprocessors. +Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in +various application domains. The ``high end'' lines concern only FPGA with high logic +capacity for complex system implementations. +This market is in significant expansion and is estimated to 914\,M\$ in 2012. +%The HPC market size is estimated today by FPGA providers at 214\,M\$. +%Using FPGA limits the NRE costs to the design cost. +%This boosts the developpment of automatic design tools and methodologies. +% +\parlf +Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, +Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand +for very high performance (HPC) primes over other requirements. They tend to use the highest +performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative +architectures and algorithms. These companies show up in different "traditional" applications and market +segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC +emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers +at 214\,M\$. +This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion +of FPGA-based solutions is limited by the lack of design automation. +\\ +\\ +Nowadays, there are no commercial or academic tools covering the whole design flow +from the system level specification to the bitstream generation neither for embedded system design +nor for HPC. + +%PC => IA et Alain +%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue +%Je le mets donc en commentaire + +%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and +%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP, +%processor, bus core, ...) as well as incorporate their own IP. +%Designers can then generate a synthesized netlist, simulation test bench and custom +%software library that reflect the hardware configuration. +%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to +%simulate the platform at a high design level (systemC). +%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation +%tool to implement designs on \altera devices (Stratix, Arria, Cyclone). +%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize +%coprocessors from a C++ description. +%Nevertheless, they can only deal with data dominated applications and they do not handle +%the platform level. +%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to +%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs. +%Designers can design and simulate a system using MATLAB and Simulink. The tool will then +%automatically generate synthesizable Hardware Description Language (HDL) code mapped to +%\xilinx pre-optimized macro-cells. +%However, this tool targets only DSP based algorithms. +%\\ +%Consequently, a designer developping an embedded system needs to master four different +%design environments: +%\begin{enumerate} +% \item a virtual prototyping environment such as SoCLib for system level exploration, +% \item an architecture compiler (such as SOPC Builder from \altera, or System generator +% from \xilinx) to define the hardware architecture, +% \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for +% coprocessor synthesis, +% \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation. +%\end{enumerate} +%Furthermore, mixing these tools requires an important interfacing effort and this makes +%the design process very complex and achievable only by designers skilled in many domains. + +\begin{center}\begin{minipage}{.9\linewidth}\textit{ +The aim of the COACH project is to integrate all these design steps into a single design framework +and to allow \textbf{pure software} developpers to design embedded systems. +}\end{minipage}\end{center} + +%PC => IA et Alain +% le paragraphe suivant est coupé collé de la section suivante 2.2 + + +\parlf +The COACH project proposes an open-source framework for mapping multi-tasks software applications +on Field Programmable Gate Array circuits (FPGA). +It aims to propose solutions to the societal/economical challenges by +providing SMEs novel design capabilities enabling them to increase their +design productivity with design exploration and synthesis methods that are placed on top +of the state-of-the-art methods. +We believe that the combination of a design environment dedicated to software developpers +and FPGA targets, +will allow small and even very small companies to propose embedded system and accelerating solutions +for standard software applications with attractive and competitive prices. +This new market may explode in the same way as the micro-computer market in the eighties, +whose success was due to the low cost of the first micro-processors (compared to main frames) +and the advent of high level programming languages which allowed a high number of programmers +to launch start-ups in software engineering. Index: /anr/section-objectif.tex =================================================================== --- /anr/section-objectif.tex (revision 289) +++ /anr/section-objectif.tex (revision 289) @@ -0,0 +1,127 @@ +\anrdoc{\begin{itemize} +\item Decrire les objectifs du projet et detailler les verrous scientifiques et + techniques a lever par la realisation du projet. Insister sur le caractÚre + ambitieux et/ou novateur de la proposition. +\item Decrire eventuellement le ou les produits finaux developpes, presenter les + resultats escomptes en proposant si possible des critÚres de reussite et + d’evaluation adaptes au type de projet, permettant d’evaluer les resultats en + fin de projet. +\end{itemize}} + +% les objectifs scientifiques/techniques du projet. +The design steps are presented figure~\ref{coach-flow}. +\ADDED{ +The end-user input is +either a HPC application (an application running on a PC that must be accelarate), +or an embedded application (a standalone application), +or a sub-system application of a larger design. +The figure shows that the design flow of embedded and sub-system applications does not differ +except in the generation step and that the design flow of HPC application just adds a +preliminary step. +} +\begin{figure}[hbtp]\leavevmode\center + \includegraphics[width=1.0\linewidth]{flow2} + \caption{\label{coach-flow} COACH design flow} +\end{figure} +\begin{description} +\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application +which remains on the PC and the SoC application which is mapped on the FPGA. +COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) +which will allow performance evaluation. +\item[SoC design:] In this phase, +COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. +The user input will consist of a process network describing the coarse grain parallelism +of the application, an instance of an architectural template +and a mapping of processes on the architectural template components. +COACH will offer different targets to map the processes: +software (the process runs as a software task on a SoC processor), +ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), +and hardware (the process is implemented as a synthesized hardware coprocessor). +\begin{SUPPRESSEDENV} +\item[Application compilation:] +Once the SoC architecture is validated through performances analysis, +COACH will generate automatically an executable containing the host application and +the FPGA bitstream. This bitstream contains +both the hardware architecture and the SoC application software. +The user will be able to launch the application by +loading the bitstream on an FPGA and running the executable on PC. +\end{SUPPRESSEDENV}\begin{ADDEDENV} +\item[Generation:] +Once the SoC architecture is validated through performances analysis, +COACH generates its bitstream in the case of HPC or embedded application, +or its IP-XACT description for its integration in the case of a sub-system application. +Both descriptions contain the hardware architecture and the application software. +Furthermore in the HPC case, an executable containing the host application is +also generated and the user will be able to launch the application by loading +the bitstream on an FPGA and running the executable on PC. +\end{ADDEDENV} +\end{description} + +% l'avancee scientifique attendue. Preciser l'originalite et le caractere +% ambitieux du projet. +%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire} + +%The main scientific contribution of the project is to unify various synthesis techniques +%(same input and output formats) allowing the user to swap without engineering effort +%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis. +%Another advantage of this framework is to provide different abstraction levels from +%a single description. +%Finally, this description is device family independent and its hardware implementation +%is automatically generated. + +% Detailler les verrous scientifiques et techniques a lever par la realisation du projet. +Hardware/Software co-design is a very complex task. To simplify it, COACH will address the +following scientific and technological barriers: +\begin{description} +\item[\textit{Design Space Exploration by Virtual Prototyping}]: + The COACH environment will allow to easily map a parallel application (formally described as + an abstract network of process and communication channels) + COACH will permit the system designer to explore the design space, and to define the best + hardware/software partitioning of the application. +\item[\textit{Integration of system level modeling and HLS tools}]: + COACH will support the automated generation of hardware accelerators when required + by using High-Level Synthesis (HLS) tools. These HLS tools will be + fully integrated into a complete system-level design environment. + Moreover, COACH will support both data and control dominated applications, + and the HLS tools of COACH will support a common language and coding style + to avoid re-engineering by the designer. + COACH will provide a tool which will automatically explore the micro-architectural + design space of coprocessor. +\item[\textit{High-level code transformation}]: + COACH will allow to optimize the memory usage, to enhance the parallelism through + loop transformations and parallelization. The challenge is to identify the coarse + grained parallelism and to generate, + from a sequential algorithm, application containing multiple communicating + tasks. COACH will adapt techniques which were developed in the 1990 for + the construction of distributed programs. However, in the context of HLS, there are + several original problems to be solved, related to the FIFO communication channels and with + memory optimization. + COACH will support code transformation by providing a source to source C2C tool. +\item[\textit{Unified Hardware/Software communication middleware}]: + COACH will rely on he SoCLib experience to implement an unified hardware/software communication + infrastructure and communication APIs (Application Programming Interface), to support + communications between software tasks running on embedded processors and dedicated + hardware coprocessors. The main issue here is to support easy migration + from a software implementation to an hardware implementation. +\item[\textit{Processor customization}]: + ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. + COACH will allow system designers to explore the various level of interactions between + the original CPU micro-architecture and its extension. It will also allow to retarget + the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis + in a complete System-level design framework. +\end{description} + +%Presenter les resultats escomptes en proposant si possible des criteres de reussite +%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en +%fin de projet. +The main result is the framework. It is composed concretely of: +a communication middleware for HPC, +5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, +Memory optimization HLS and ASIP), +3 architectural templates that are synthesizable and that can be prototyped, +one design space exploration tool, +1 operating systems (DNA/OS). +\\ +The framework functionalities will be demonstrated with the demonstrators +(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 +page~\ref{subtask-tutorial}). Index: /anr/section-position.tex =================================================================== --- /anr/section-position.tex (revision 289) +++ /anr/section-position.tex (revision 289) @@ -0,0 +1,231 @@ +\anrdoc{Preciser:\begin{itemize} +\item positionnement du projet par rapport au contexte developpe precedemment : + vis- a-vis des projets et recherches concurrents, complementaires ou + anterieurs, des brevets et standards... +\item indiquer si le projet s'inscrit dans la continuite de projet(s) anterieurs + deja finances par l'ANR. Dans ce cas, presenter brievement les resultats acquis, +\item positionnement du projet par rapport aux axes thematiques de l'appel a projets, +\item positionnement du projet aux niveaux europeen et international. +\end{itemize}} + +% Relevance of the proposal +%The COACH proposal addresses directly the \emph{Embedded Systems} item of +%the ARPEGE program. + +%PC => IA et ALain +%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1 + +%It aims to propose solutions to the societal/economical challenges by +%providing SMEs novel design capabilities enabling them to increase their +%design productivity with design exploration and synthesis methods that are placed on top +%of the state-of-the-art methods. +%This project proposes an open-source framework for mapping multi-tasks software applications +%on Field Programmable Gate Array circuits (FPGA). +%%% +\parlf +COACH will contribute to build an open design and run-time +environment, including communication middleware and tools to support +developers in the production of embedded software, through all phases of the software lifecycle, +from requirements analysis downto deployment and maintenance. +More specifically, COACH focuses on: +\begin{itemize} +\item High level methods and concepts (esp. requirements and architectural level) for system +design, development and integration, addressing complexity aspects and modularity. +\item Open and modular design environments, enabling flexibility and extensibility by +means of new or sector-specific tools and ensuring consistency and traceability along the +development lifecycle. +\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive +environment, suitable for co-operative and distributed development. +\end{itemize} +COACH outcome will contribute to strengthen Europe's competitive position by developing +technologies and methodologies for product design, focusing (in compliance with the +%scope of the above program) on technologies, engineering methodologies, novel tools, +%methods which facilitate resource use efficiency. The approaches and tools to be developed +%in COACH will enable new and emerging information technologies for the development, +%methods which facilitate resource use efficiency. The COACH approaches and tools +scope of the above program) on technologies, engineering methodologies, novel tools +which facilitate resource use efficiency. The COACH approaches and tools +will enable new and emerging information technologies for the development, +manufacturing and integration of devices and related software into end-products. +%%% +\parlf\noindent +The COACH project will benefit from a number of previous recent projects: +\begin{description} + \item[SOCLIB] + The SoCLib ANR platform (2007-2009) is an open infrastructure developped by + 10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 + industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). + It supports system level virtual prototyping of shared memory, multi-processors + architectures, and provides tools to map multi-tasks software application on these + architectures, for reliable performance evaluation. + The core of this platform is a library of SystemC simulation models for + general purpose IP cores such as processors, buses, networks, memories, IO controller. + The platform provides also embedded operating systems and software/hardware + communication middleware. + The synthesisable VHDL models of IPs are not part of the SoCLib platform, and + COACH will enhance SoCLib by providing the synthesisable VHDL models required + for FPGA synthesis. + \item[ROMA] The ROMA ANR project \cite{roma} + involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D, + proposes to develop a reconfigurable processor, exhibiting high + silicon density and power efficiency, able to adapt its computing + structure to computation patterns that can be speed-up and/or + power efficient. %The ROMA project study a pipeline of + %evolved low-power coarse grain reconfigurable operators to avoid + %traditional overhead, in reconfigurable devices, related to the + %interconnection network. + The project will borrow from the ROMA + ANR project and the ongoing joint INRIA-STMicro + Nano2012 project to adapt existing pattern extraction algorithms + and datapath merging techniques to ASIP synthesis. +% and datapath merging techniques to the synthesis of customized +% ASIP processors. + \item[TSAR] + The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a +% The TSAR MEDEA+ project (2008-2010) targets the design of a + scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib + plaform for virtual prototyping. COACH will benefit from the synthesizable VHDL + models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). + \item[BioWic] + On the HPC application side, we also hope to benefit from the experience in + hardware acceleration of bioinformatic algorithms/workfows gathered by the + CAIRN group in the context of the ANR BioWic project (2009-2011), so as to + be able to validate the framework on real-life HPC applications. +\end{description} +%%% +\parlf\noindent +The laboratories involved in the COACH project have a well estabished expertise +%in the following domains: +in the domains: +\begin{itemize} + \item + In the field of High Level Synthesis (HLS), the project + leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project + developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped + by the \upmc and \tima laboratories. + \item + Regarding system level architecture, the project is based on the know-how + acquired by \upmc and \tima in the framework of various projects + in the field of communication architectures for shared memory multi-processors systems + (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA). + As an example, the DSPIN project is now used in the TSAR project. + \item + Regarding Application Specific Instruction Processor (ASIP) design, the + CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of + expertise in the domain of retargetable compiler + (Armor/Calife~\cite{CODES99} since 1996, and the Gecos + compilers~\cite{ASAP05} since 2002). +\item + In the field of compilers, the \lip Compsys group was founded in 2002 + by several senior researchers with experience in + high performance computing and automatic parallelization. They have been + among the initiators of the polyhedral model, a theory which serve to + unify many parallelism detection and exploitation techniques for regular + programs. It is expected that the techniques developped by \lip for + parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb}, + process construction \cite{Feau:96} and memory management \cite{bee} + will be very useful as a front-end for HLS tools. +\end{itemize} +%%% +\parlf\noindent +The COACH project answers to several of the challenges found in different axis of the +call for proposals.%Keywords of the call are indicated below in italic writing. +\begin{description} +\item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\ +COACH will address new embedded systems architectures by allowing the design of +Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design +constraints and objectives (real-time, low-power). It will permit designing complex SoC +based on IP cores (memory, peripherals...), +running Embedded Software, as well as an Operating System with associated middleware and +API and using hardware accelerator automatically generated. It will also permit to use +efficiently different dynamic system management techniques and re-configuration mechanisms. +\textbf{Thereby COACH well corresponds to axis 1}. +% +\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\ +COACH will address High-Performance Computing (HPC) by helping designers to accelerate an +application running on a PC. +By providing tools that translate high level language programs to FPGA +configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the +PC bus (through a communication link like PCI/X). +Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance +as well as reducing the required area. +\textbf{Thereby COACH partially corresponds to axis 2}. +% +% IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et +% IA2PC: secondaire. +%VERS 3 +%\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\ +%Manufacturing technology employs more and more SoC. +%COACH will permit to design such complex digital systems. +%\textbf{Thereby COACH indirectly answers to axis 3 too}. + + +%\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\ +%VERS 1 +%Future control applications employ more and more SoC. +%Application domains for such systems are for example the automotive domain, as well as the +%aerospace and avionics domains. +%In all cases, high performance and real time requirements are combined with +%requirements to low power, low temperature, high dependability, and low cost.\\ +%Similary manufacturing, security and safety technologies require also more and more +%computation power. +%VERS 2 pour gagner de la place +%Manufacturing, controling, security and safety technologies employ more and more SoC. +%COACH will permit to design such complex digital systems. +%\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}. + +%\end{description} + +\item [Axis 3] \textit {Robotique et contr\^{o}le/commande}: + +COACH will address robotic and control applications by +allowing to design complex systems based on MPSoC architecture. +Like in the consumer electronics domain, future control applications +will employ more and more SoC for safety and security applications. +Application domains for such systems are for example automotive +or avionics domains (e.g. collision-detection, intelligent navigation...). +Manufacturing technology will also increasingly need high-end vision analysis and high-speed +robot control. +\textbf{Thereby COACH indirectly answers to axis 3}. + +\item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}: + +The results of the COACH project will help users to build cryptographic secure systems implemented in +hardware or both in software/hardware in an effective way, substantially enhancing the +process productivity of the cryptographic algorithms hardware synthesis, improving the +quality and reducing the design time and the cost of synthesised cryptographic devices. +\textbf{Thereby COACH indirectly answers to axis 5}. + +\end{description} + +% IA2PC: 1) je ne vois pas trop ce que ca fait la. +% IA2PC: 2) c'est deja dans le 2.1 pour le small business. +% IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense +% IA2PC toujours que le large business est encore vise par COACH. +% IA2PC Alain a enleve toute reference sur ce large business. Sa raison est + +% IA2PC politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille +% IA2PC le message. Je partage assez son avis, la version actuelle est + claire que +% IA2PC celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses +% IA2PC boites. +% IA2PC +% IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large +% IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans +% IA2PC les sections precedentes. +% +% VERS 2 pour gagner de la place je l'enleve + +%PC2IA ok pas de probleme + +% COACH technologies can be used in both large and small business, as they will permit users to design +% embedded systems which meet a wide range of requirements: from low cost and low power consuming +% devices to very high speed devices, based on parallel computing. For enterprises that will use embedded +% systems designed via the approaches and tools targeted by COACH, there is the potential for greater +% efficiency, improved business processes and models. The net results: lower costs, faster response times, +% better service, and higher revenue. +%\parlf +Finally, it is worth to note that this project covers priorities defined by the commission +experts in the field of Information Technolgies Society (IST) for Embedded +Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity +and allowing to apply efficiently applications and various products on embedded platforms, +considering resources constraints (delays, power, memory, etc.), security and quality +services$>>$}. Index: /anr/section-project-description.tex =================================================================== --- /anr/section-project-description.tex (revision 289) +++ /anr/section-project-description.tex (revision 289) @@ -0,0 +1,151 @@ +\anrdoc{% +Presentez le programme scientifique et justifiez la decomposition en taches du +programme de travail en coherence avec les objectifs poursuivis.\\ +Utilisez un diagramme pour presenter les liens entre les differentes taches (organigramme technique)\\ +Les taches representent les grandes phases du projet. Elles sont en nombre +limite.\\ +Le cas echeant (programmes exigeant la pluridisciplinarite), demontrer +l'articulation entre les disciplines scientifiques.\\ +N'oubliez pas les activites et actions correspondant à la dissemination et à la valorisation.} + + +\begin{figure}\leavevmode\center +\includegraphics[width=.8\linewidth]{architecture-csg} +\caption{\label{archi-csg} Software architecture for digital system generation} +%\end{figure}\begin{figure}\leavevmode\center +\mbox{}\vspace*{1ex}\\ +\includegraphics[width=1.0\linewidth]{architecture-hls} +\caption{\label{archi-hls} Software architecture of hardware accellerator synthesis} +%\end{figure}\begin{figure}\leavevmode\center +\mbox{}\vspace*{1ex}\\ +\includegraphics[width=.8\linewidth]{architecture-hpc} +\caption{\label{archi-hpc} Performance analysis of a HPC partitionning} +\end{figure} +% +Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} +summarize the software architecture of the COACH framework we will develop. +In figures, the dotted boxes are the softwares or formats that COACH +has to provide and to support. +\parlf +For the system generation presented in figure~\ref{archi-csg}, the conductor +is the tool \verb!CSG! (COACH System Generator). Its inputs are a process +network describing the target application and the synthesis parameters. +The main parameters are the target hardware architectural template +with its instantiation parameters, the hardware/software mapping of the +tasks, the FPGA device and design constraints. +\verb+CSG+ thus requires an architectural template library, an operating system +library, two system hardware component (CPU, memories, BUS...) libraries +(one for synthesis, one for simulation). +For generating the coprocessor of a task mapped as hardware, \verb+CSG+ +controls the HAS tools described below. +From these inputs \verb!CSG! can generate the entire system (both software and +hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger +design or} +as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the +design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and +launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the +FPGA device\footnote{Additional partial bitstreams are generated in case of + dynamic partial reconfiguration}. + \begin{ADDEDENV} + \\ + Furthermore the architecture template and hardware component libraries will be described + under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other + architecture or the enhancement of existing template with IP. + \end{ADDEDENV}% +\parlf +The software architecture for HAS is presented in figure~\ref{archi-hls}. +The input is a single task of the process network. The HAS tools do not work +directly on the C++ task description but on an internal format called +\xcoach generated by a plugin into the GNU C compiler (GCC). +This will allow on the one hand to insure that all the tools will +accept the same C++ description and on the other hand make possible +their chaining. The front-end tools read a \xcoach description and generate +a new \xcoach description that exibits more parallelism or implement +specific instructions for ASIP. The back-end tools read an \xcoach +description and generate an \xcoachplus description. This is an \xcoach +description annotated with hardware information (scheduling, binding) required by +the VHDL and systemC drivers. +Furthermore, the back-end tools uses a macro-cell library (functional and memory +unit). +\parlf +In addition to digital system design, HPC requires a supplementary +partitioning step presented in figure~\ref{archi-hpc}. The designer +splits the initial application (tag 1) in two parts: one still on the PC and the +other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data +through communication primitives (tag 2) implemented in a library. +To evaluate the relevance of the partitioning, the designer can build a +simulator. Once the partitioning is validated, the design of the FPGA part +is done through \verb!CSG! (figure~\ref{archi-csg}). +\parlf +The project is split into 8 tasks numbered from 1 to 8. They are described +in short below and in detail in section \ref{task-description}. +\begin{description} +\item[Task-1: \textit{Project management}] + This task relates to the monitoring of the COACH project. +\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the + project such as the defintion of the COACH inputs and outputs, + the internal formats (i.e. \xcoach and \xcoachplus) and their associated tools, + the architectural templates and the design flow. +\item[Task-3: \textit{System generation}] This task addresses the prototyping and + the generation of digital system. Apart from HAS that belongs to task 3 + and 4, its components are those presented figure~\ref{archi-csg} + (e.g. \verb!CSG!, operating systems). +\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities: + optimization of the memory usage, parallelism enhancement through loop + transformations, coarse grain parallelization and ASIP generation. +\item[Task-5: \textit{HAS back-end}] This task groups two functionalities: + High-Level Synthesis of data dominated description and HLS of control + dominated description. + This task contains also the development of a frequency adaptator + that will allow the coprocessors to respect the processor and the bus + frequency. +\item[Task-6: \textit{PC/FPGA communication middleware}] + This task pools the features dedicated to HPC. These are mainly the + validation of the partitioning (see figure~\ref{archi-hpc}), the sytem drivers for + both PC and FPGA-SoC sides, the hardware communication components and + the support for dynamic partial reconfiguration. +\item[Task-7: \textit{Industrial demonstrators}] + This task groups the demonstrators of the COACH project. + Most of them are industrial applications that will be developped within + the COACH framework. + Others consist in integrating the COACH framework as a driver of + industrial proprietary design tools. +\item[Task 8: \textit{Dissemination}] + This task concerns the diffusion of the project results. + It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!, + \verb!T0+24! and \verb!T0+36!), the publication of a tutorial and user manuals on a WEB site, the publication + of research papers in international journals and conferences and the organization of workshops and tutorials in + international conferences. +\end{description} +% +\begin{figure}\leavevmode\center +%\includegraphics[width=.4\linewidth]{dependence-task} +\includegraphics[width=0.70\linewidth]{dependence-task-h} +\caption{\label{dependence-task}Task dependencies} +\end{figure} +Figure~\ref{dependence-task} presents the tasks dependencies. +"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$. +The more bold the arrow, the more important is the impact. +The graph shows: +\begin{itemize} +\item Even though $T4$ and $T5$ functionalities are complementary, +their developments are independent (thanks to the \xcoach internal format). +\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may work +without $T4$ and $T5$ if targeted digital systems do not include hardware +accelerators. +\item $T3$ strongly impacts $T6$ but $T3$ does not depend at all on +$T6$. Hence demonstrators ($T7$) of embedded system would not be impacted if +$T6$ would fail. +\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) and is at the heart of +the COACH project. +\item The demonstrators developped in $T7$, of course strongly depend on the achievements +of the previous tasks ($T2$, $T3$, $T4$, $T5$, $T6$). +\item $T8$ and $T1$ depend on and impact all the other tasks. +\end{itemize} +This organisation offers enough robustness to insure the success of the +project except for the specification task $T2$. +The only critical task in this chart is $T2$. \label{xcoach-problem} +However, the partners met +12 times (a one-day meeting per month) during the last year: 10 meetings to exchange and work on scientific +and technical aspects and 2 meetings to prepare the project proposal. This gives us a high degree of confidence +that $T2$ will be completed in time. Index: /anr/section-project-management.tex =================================================================== --- /anr/section-project-management.tex (revision 289) +++ /anr/section-project-management.tex (revision 289) @@ -0,0 +1,70 @@ +\anrdoc{Preciser les aspects organisationnels du projet et les modalites de +coordination (si possible individualisation d’une tache de coordination).} + +\begin{description} +\item[Project management structure] +Each task is assigned to a Task Leader. +The Task Leaders assist the project leader in the technical organization, effort +management, of the co-operation and the reporting of the progress. +A steering committee is composed by task leaders and the project leader. +The steering committee has a monthly conference call and is in charge of conflict +management if necessary. +Each task leader has to report on the main high-lights, major +opportunities and problems according to the work-plan. +The redaction of the 6-month reports is the responsability of the steering committee. +Therefore, each Partner has the responsibility to monthly inform the task Leaders of the +current development of the \ST he has in charge. +COACH will be organized in 8 tasks whose interactions are presented in +Figure~\ref{dependence-task}. + +\item[Scientific and Technical Reports] +For every yearly review, a written progress report for each deliverable has to be +provided by the task leader to the coordinator for integration in the contractual reports. + +\item[Management of knowledge, Intellectual Property Right (IPR) and Results Exploitation] +The partners will have to work under eventual NDA constraints. +Prior Intellectual Property remains property of the concerned partners. +The exploitation of the results obtained in the project and by each partner involved in the consortium will +follow the rules written in the articles of the Consortium Agreement accepted and signed by +each partner at most 6 months after the project kick-off. +To manage the exploitation and dissemination plan within the project, six +monthly meetings will analyze the intentions from the consortium (patent, publication...). + +\item[Management Tools] +In order to permit a good management, before the kick-off meeting, +each partner will have to identify (name, address, phone, fax and e-mail): +\begin{itemize} + \item the financial and administrative contact person, + \item the scientific and technical contact person, + \item all participants to the project. +\end{itemize} +A complete and detailed list will be communicated to each partner and to +the public Authority. The partners will construct mailing lists for +day-to-day communication. + +The first task will be the redaction of a Consortium Agreement, +dealing mainly with all aspects of the relations +between partners, including legal aspects, property rights and further +exploitation of the results. This document will be submitted to the +partner's financial and legal departments, and will define the management +rules (decision level, reporting systems, red flag cases). +A first draft of this document will be submitted to each partner +during the kick-off meeting. + +\item[Project follow-ups] +The basic communication between single project partners will be carried out by means of an Information System (web site), which will be developed and introduced at the very beginning of the project implementation. +All scientific and administrative data related to the project will be collected and +treated within a specific e-management plate-form accessible directly by the project web +site by an individual login and pass-word. +The web site will have a few levels of accessibility starting with completely free access, +open to broad public up to internal materials available only for members of the consortium +for the e-management area. +This communication tools will permit to perform all the reports and to follow as well as +possible all the tasks. + +\item[Project monitoring] +For this project format and size, a 12 months review by ANR, based on a yearly progress +report incorporating milestones reports and deliverables, seems optimum. +The internal consortium meetings will be every six months, including a kick-off meeting at the +start of the project, in our eyes the most important of all, as it phases the partners for the start of the project. +\end{description} Index: /anr/section-project-task-schedule.tex =================================================================== --- /anr/section-project-task-schedule.tex (revision 289) +++ /anr/section-project-task-schedule.tex (revision 289) @@ -0,0 +1,116 @@ +\anrdoc{\begin{itemize} +\item Presenter sous forme graphique un echeancier des differentes taches +et leurs dependances (diagramme de Gantt par exemple). +\item Presenter un tableau synthetique de l'ensemble des livrables du +projet (numero de tache, date, intitule, responsable). +\item Preciser de facon synthetique les jalons scientifiques et/ou +techniques, les principaux points de rendez-vous, les points bloquants ou +aleas qui risquent de remettre en cause l'aboutissement du projet ainsi que +les reunions de projet prevues.\end{itemize}} + +\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90} +\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99} +\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7} +\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7} +\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4} +\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24} +\def\ganttlabelstyle#1{\begin{small}#1\end{small}} +\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}} + +%\begin{figure}\leavevmode\center +%\hspace*{-.6cm} +%\input{gantt.tex} +%\caption{\label{gantt}Gantt diagram of deliverables} +%\end{figure} + +\begin{figure}\leavevmode\center +\hspace*{-.4cm}%\vspace{-1.5cm} +\input{gantt1.tex} +\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)} +\end{figure} + +\begin{figure}\leavevmode\center +\hspace*{-.4cm}%\vspace{-1.5cm} +\input{gantt2.tex} +\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)} +\end{figure} + +The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project. +Before the final release (T0+36), there are 4 milestones (red lines on the figures) at +$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent +deliverables. +\begin{description} +\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of + the demonstatrors as a reference software. +\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are + written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC. + The main restrictions are: + 1) Only the neutral architectural template is supported, + 2) HAS is not available (but prototyping with virtual coprocessors is available), + 3) Enhanced communication schemes are not available. + 4) ASIP compilation flow is not available. +\item[Milestone 3 ($T0+18$)] The second COACH release. At this step most of the COACH + features are availables. A preliminary version of the ASIP synthesis flow is supported, for a + simple extensible MIPS model. The main restriction is that COACH can not yet + generate FPGA-SoC for \altera and \xilinx architectural templates. + The others restriction is that the HAS tools are not yet fully operational. +\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is + supported. + The main restriction are: + 1) The backend HAS tools have not been yet enhanced, + 2) Dynamic partial reconfiguration is not supported, + 3) NIOS processor instruction set extension is supported, but only for user specified patterns. +\item[Final Release ($T0+36$)] + +\end{description} +This organisation allows the project to globally progress step by step mixing development +and demonstrator deliverables. +Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility +at the integration phase is significantly reduced. +\par +The risks that have been identified at the beginning of the project are the following: +\begin{description} +\item[\xcoach format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})] + Partners have to agree on a convenient exchange format for all tools involved. + Because all the HAS tools rely on it, the \xcoach format specification is a + crucial step. There are no work-around but as mentionned in + section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it + for a full year and a preliminary document already exists. +%\item[\xcoachplus format (\novers{\specXcoachDoc}, +% \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] +% Its aim is the generation of the coprocessors (hardware \& prototyping model). +% By centralizing the coprocessor generation, it guarantees their functioning +% independently of the used HAS tools. +% Our experience with UGH and GAUT give us confidence in the succes of this +% task. +\item[Virtual prototyping of \altera \& \xilinx architectural templates (\novers{\csgImplementation})] + The SoCLib component library contains several SystemC models used for the virtual + prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores). + Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped. + If the workload of this simulation model development is too important, virtual prototyping + of those architectural templates will not be directly supported. + The three architectural templates being quite similar, the virtual + prototyping will use the neutral architectural template. +\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})] + If one of these tasks is impossible or too important or leads to inefficiency, + it will be abandoned. + In this case, the neutral architectural template will not be available for HPC and + a SystemC VCI model corresponding to the PCI/X IP will be developped to allow + virtual prototyping. +\end{description} +\parlf +Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}. +\begin{figure}\leavevmode\center +{ +\fontsize{7pt}{9pt}\selectfont +\settowidth\desclen{XILINX RTL optimisation (5)} +\def\Sformat#1{\textsc{#1}} +%\hspace*{-2.5mm} +\begin{minipage}{1.0\linewidth} +\input{table_livrable_01.tex} +\hfill\hspace*{1mm}\hfill +\input{table_livrable_02.tex} +\end{minipage} +} +\caption{\label{all-delivrables}All the deliverables} +\end{figure} Index: /anr/section-ressources.tex =================================================================== --- /anr/section-ressources.tex (revision 289) +++ /anr/section-ressources.tex (revision 289) @@ -0,0 +1,302 @@ +\anrdoc{On présentera ici la justification scientifique et technique des moyens +demandés dans le document de soumission A par chaque partenaire et +synthétisés à l'échelle du projet dans la fiche «Tableaux récapitulatifs» +du document de soumission A.\\ +Chaque partenaire justifiera les moyens qu'il demande en distinguant les +différents postes de dépenses.\\ +Pour chaque partenaire on precisera: +\begin{itemize} +\item Equipment: 1) Préciser la nature des équipements* et justifier le + choix des équipements. 2) Si nécessaire, préciser la part de financement + demandé sur le projet et si les achats envisagés doivent être complétés + par d'autres sources de financement. Si tel est le cas, indiquer le + montant et l'origine de ces financements complémentaires.\\ + * Attention: Un devis sera demandé si le projet est retenu pour + financement. +\item Personnel costs + 1) Le personnel non permanent (thÚses, post- doctorants,CDD...) + financé sur le projet devra être justifié. + 2) Fournir les profils des postes à pourvoir pour les personnels à + recruter (1/2 page maximum par type de poste) + 3) Pour les thÚses, préciser si des demandes de bourse de thÚse sont + prévues ou en cours, en préciser la nature et la part de financement + imputable au projet. +\item Subcontracting. Préciser: 1) la nature des prestations + 2) le type de prestataire. +\item Travel. Préciser: 1) les missions liées aux travaux d'acquisition + sur le terrain (campagnes de mesures), + 2) les missions relevant de colloques, congrÚs. +\item Costs justified by internal procedures of invoicing. Préciser la nature + des prestations. +\item Other expense. Toute dépense significative relevant de ce poste + devra être justifiée. +\end{itemize}} + +\def\resstablestyletitle#1{\begin{small}{\textit{#1}}\end{small}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 1: \irisa} + +\begin{description} +\item [Equipment] + No specific equipment acquisition. +\item [Personnel costs] The faculty members involved in the project + are François Charot (INRIA researcher), Steven Derrien (associate + professor), Christophe Wolinski (professor) and Charles Wagner + (research engineer). The non-permanent personal required is a PhD + student that will mainly work on ASIP generation. We are looking for + a profile with strong informatic skills and good knowledge in + computer architecture. + \parlf + The table below summarizes the manpower in \hommemois by tasks for both permanent and + non-permanent personnels. The detail by deliverables is given in + figure~\ref{table-livrables-1}. + The non-permanent personnels costs represent {48\%} of the personnal + costs. The requested funding for non permanent personnels is 100\% of + the total ANR requested funding. + \begin{center}\input{table_inria_cairn_short.tex}\end{center} +\item [Subcontracting] + No subcontracting costs. +\item [Travel] + The travel costs are associated to project meeting as well as participation to + conferences. The travel costs are estimated to {7,5\%} of the total + requested ANR funding. +\item [Expenses for inward billing] + The costs justified by internal invoicing procedures are evaluated to 4\% of the total + requested ANR funding. +\end{description} + + +\subsection{Partner 2: \lip} + +\begin{description} +\item [Equipment] + No specific equipment acquisition. The costs for depreciation of + workstations is evaluated to 4\% of the total requested ANR funding. +\item [Personnel costs] + The faculty members involved in the project are an emeritus + professor at ENS Lyon (Paul Feautrier) and a research associate + (CR2) at INRIA Rh\^one-Alpes (Christophe Alias). The non-permanent + personel required is a PhD student that will work on network process + generation from polyhedral loops, then on extensions to + non-polyhedral loops. We are looking for a student with both + theoretical and practical skills, that will be able to get a + sufficient understanding of the polyhedral techniques and to produce + a working implementation. + \parlf + The table below summarizes the \hommemois by + deliverables and tasks for both permanent and non-permanent + personnels. The non-permanent personnels costs represent 26\% of + the personnal costs. The requested funding for non + permanent personnels is 100\% of the total ANR requested funding. + \begin{center}\input{table_inria_compsys_full.tex}\end{center} +\item [Subcontracting] + No subcontracting costs. +\item [Travel] + The travel costs are associated to project meeting as well as + participation to conferences. The travel costs are estimated to 20\% + of the total requested ANR funding. +\item [Expenses for inward billing] + The costs justified by internal invoicing procedures are evaluated + to 4\% of the total requested ANR funding. +\end{description} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 3: \tima} + +\begin{description} +\item [Equipment] + No specific equipment acquisition. +\item [Personnel costs] + The permanent personnels involved in the project are professor and assistant professor + (Fr\'ed\'eric P\'etrot and Olivier Muller). + The non permanent personnels are Phd students and post-doc researchers. + Related costs are estimated in \hommemois. + One phd student (Adrien Prost-Boucle), funded by the french ministry of research, will + be working on the project. + One 100\% funded phd student will be hired in september 2010. A post-doc researcher will + be hired at the end of 2011 for one year and an half. + The PhD student will mainly work on the evolution of UGH HLS tool. Thus, we are looking + for a profile with strong informatic skills and good knowledge in computer architecture. + The post-doc will mainly work on dynamic reconfiguration and HPC. The required profile + will be more oriented on computer architecture and advanced digital design. + \parlf + The table below sumarizes the man power in \hommemois by tasks for both permanent and + non-permanent personnels. The detail by deliverables is given in + figure~\ref{table-livrables-1}. + The requested funding for personnels represent 50\% of the total personnal costs. + The requested funding for non permanent personnels is 85\% of the total ANR requested + funding. + \begin{center}\input{table_tima_short.tex}\end{center} +\item [Subcontracting] + No subcontracting costs. +\item [Travel] + The travel costs are associated to project meeting as well as participation to + conferences. The travel costs are estimated to 11\% of the total requested ANR funding. +\item [Expenses for inward billing] + The costs justified by internal invoicing procedures are evaluated to 4\% of the total + requested ANR funding. +\end{description} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 4: \ubs} + +\begin {description} +\item [Equipment] + In order to validate the design flow project, the Lab-STICC laboratory will buy FPGA + developpement boards. The cost for these FPGA boards is estimated to 3\% of the total + ANR funding. +\item [Personnel costs] + The faculty members involved in the project are associate professors (Philippe COUSSY, + Cyrille CHAVET) or research engineers (Dominique HELLER). All non-permanent personnel + costs are estimated in \hommemois for senior researchers (post-doc or research + engineers). + \parlf + The table below sumarizes the man power in \hommemois by tasks for both permanent and + non-permanent personnels. The detail by deliverables is given in + figure~\ref{table-livrables-2}. + The non-permanent personnels costs represent 50\% of the personnal costs. + The requested funding for non permanent personnels is about 83\% of the total ANR + requested funding. + \begin{center}\input{table_ubs_short.tex}\end{center} +\item [Subcontracting] + No subcontracting costs. +\item [Travel] + The travel costs are associated to management and meeting as well as participation to + conferences. The travel costs are estimated to 10\% of the total requested ANR funding. +\item [Expenses for inward billing] + The costs justified by internal invoicing procedures are evaluated to 4\% of the total + requested ANR funding. +\end {description} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 5: \upmc} + +\begin{description} +\item[Equipment] + No specific equipment acquisition is required for this project. + The costs for depreciation of workstations and pre-existing FPGA boards are evaluated + to 7\% of the total requested ANR funding. +\item[Personnel costs] + The permanent personnels involved in the project are professors or assistant + processors (Alain Greiner and Ivan Aug\'e). + All non permanent personnel costs are estimated in \hommemois for senior researchers + (post-doc or research engineers). + The table below sumarizes the man power by tasks in \hommemois for both permanent and + non-permanent personnels. + The detail by deliverables is given in figure~\ref{table-livrables-2}. + The non-permanent personnels costs represent 50\% of the personnal costs. + The requested funding for non permanent personnels is 79\% of the total ANR + requested funding. + \begin{center}\input{table_upmc_short.tex}\end{center} +\item[Subcontracting] + No subcontracting costs. +\item[Travel] + The travel costs are associated to management and coordination meeting as + well as participation to conferences. The travel costs are estimated + to 10\% of the total requested ANR funding. +\item[Expenses for inward billing] + The costs justified by internal invoicing procedures are evaluated to 4\% + of the total requested ANR funding. +\end{description} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 6: \mds} + +\mustbecompleted{A COMPLETER: Emmanuel ....} +\begin{ADDEDENV} +\begin{description} +\item[Equipment] + No specific equipment acquisition is required for this project. +\item[Personnel costs] + \xilinx employees involved in the project are permanent Software Engineers. + The man power detail in \hommemois by deliverables is given in + figure~\ref{table-livrables-1} and a sumary by task in the following table. + \begin{center}\input{table_mds_short.tex}\end{center} +\item[Subcontracting] + No subcontracting costs. +\item[Travel] + The travel costs are associated to project meeting as well as participation to + conferences. The travel costs are estimated to 2\% of the total requested ANR funding. +\item[Expenses for inward billing] none +\item[Other working costs] none +\end{description} +\end{ADDEDENV} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 7: \bull} + +\begin{description} +\item[Equipment] + Acquisition of a FPGA development board will represent the main equipment cost for + Bull in COACH. It is estimated at about 5\% (tbc) of the total funding. +\item[Personnel costs] + A permanent engineer will be assigned full time to the project for a duration of 20 + months as shown in the table below that gives the man power in \hommemois: + \begin{center}\input{table_bull_full.tex}\end{center} +\item[Subcontracting] + No subcontracting costs. +\item[Travel] + Application of a standard 10\% of the total funding to travel costs. +\item[Expenses for inward billing] + Costs justified by inward billing are estimated to about 5\% of the total funding. +\item[Other working costs] none +\end{description} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 8: \thales} + +\begin{description} +\item[Equipment] + In order to validate the design flow,TRT will buy FPGA developpement boards. The cost + for these FPGA boards is estimated to 10 k\euro (6\% of the total ANR funding). +\item[Personnel costs] + The effort to adapt SPEAR DE to generate the input files to COACH framework is + estimated to 13 \hommemois. + The effort to describe and develop the application is estimated to 14 \hommemois. + Finally we need one \hommemois for the partiticipation to the global specification in task 2. + This is sumarized in the table below: + \begin{center}\input{table_thales_full.tex}\end{center} +\item[Subcontracting] + No subcontracting costs. +\item[Travel] + The travel costs are associated to meeting, plenaries as well as participation to + conferences. The travel costs are estimated to 10 k\euro. The travel costs are estimated to + 5\% of the total requested ANR funding. +\item[Expenses for inward billing] none +\item[Other working costs] none +\end{description} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +\begin{landscape} +\begin{figure} +\begin{small} +\settowidth\desclen{XILINX RTL optimisation (5)} +\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} +\begin{minipage}[b]{.47\linewidth}\center +\input{table_inria_cairn_full.tex}\vspace{.5ex}\\ \irisa \vspace{2.5ex}\\ +\input{table_mds_full.tex}\vspace{.5ex}\\ \mds \\ +\end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center +\input{table_tima_full.tex}\vspace{.5ex} \\ \tima +\end{minipage} +\end{small} +\caption{\label{table-livrables-1} Man power in \hommemois for the deliverables (1)} +\end{figure} +% +\begin{figure} +\begin{small} +\settowidth\desclen{XILINX RTL optimisation (5)} +\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} +\begin{minipage}[b]{.47\linewidth}\center +\input{table_ubs_full.tex}\vspace{.5ex}\\ \ubs \vspace{2.5ex}\\ +%\input{table_thales_full.tex}\vspace{.5ex}\\ \thales \\ +\end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center +\input{table_upmc_full.tex}\vspace{.5ex} \\ \upmc +\end{minipage} +\end{small} +\caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (2)} +\end{figure} +\end{landscape}