Index: /anr/Makefile =================================================================== --- /anr/Makefile (revision 290) +++ /anr/Makefile (revision 291) @@ -7,6 +7,8 @@ architecture-csg.pdf architecture-hls.pdf architecture-hpc.pdf \ dependence-task-h.pdf \ - task-0.tex task-1.tex task-2.tex task-3.tex \ - task-4.tex task-5.tex task-6.tex task-7.tex \ + task-management.tex task-backbone.tex \ + task-csg.tex task-frontend.tex \ + task-backend.tex task-hpc.tex \ + task-demonstrator.tex task-dissemination.tex \ section-project-task-schedule.tex \ section-dissemination.tex \ Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 290) +++ /anr/anr.tex (revision 291) @@ -62,5 +62,6 @@ \def\bull{BULL\xspace} \def\Sbull{\Sformat{BULL}\xspace} \def\thales{THALES\xspace} \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales -\def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace} +\def\mdslong{MAGILLEM DESIGN SERVICES\xspace} +\def\mds{MAGILLEM\xspace} \def\Smds{\Sformat{MDS}\xspace} \def\altera{ALTERA\xspace} \def\Saltera{\Sformat{ALTE}\xspace} @@ -213,28 +214,12 @@ \end{description} -\subsubsection{Task 1: \textit{Project management}} -\input{task-0} - -\subsubsection{Task 2: \textit{\Backbone}} -\input{task-1} - -\subsubsection{Task 3: \textit{System generation}} -\input{task-2} - -\subsubsection{Task 4: \textit{HAS front-end}} -\input{task-3} - -\subsubsection{Task 5: \textit{HAS back-end}} -\input{task-4} - -\subsubsection{Task 6: \textit{PC/FPGA communication middleware}} -\input{task-5} - -\subsubsection{Task 7: \textit{Industrial demonstrators}} -\input{task-6} - -\subsubsection{Task 8: \textit{Dissemination}} -\label{task-7} -\input{task-7} +\subsubsection{Task 1: \textit{Project management}} \input{task-management.tex} +\subsubsection{Task 2: \textit{\Backbone}} \input{task-backbone.tex} +\subsubsection{Task 3: \textit{System generation}} \input{task-csg.tex} +\subsubsection{Task 4: \textit{HAS front-end}} \input{task-frontend} +\subsubsection{Task 5: \textit{HAS back-end}} \input{task-backend.tex} +\subsubsection{Task 6: \textit{PC/FPGA communication middleware}}\input{task-hpc} +\subsubsection{Task 7: \textit{Industrial demonstrators}} \input{task-demonstrator.tex} +\subsubsection{Task 8: \textit{Dissemination}} \input{task-dissemination.tex} % 3.4 Index: r/task-0.tex =================================================================== --- /anr/task-0.tex (revision 290) +++ (revision ) @@ -1,59 +1,0 @@ -\begin{taskinfo} -\let\MDS\leader -\let\ALL\enable -\end{taskinfo} -% -\begin{objectif} -This task relates to the monitoring of the COACH project. Its main objectives are: -\begin{itemize} -\item To ensure the appropriate progress of the project, -\item To coordinate the scientific and technical cooperation between the partners, -\item To manage and monitor the scientific and technical work and progress in the tasks, -\item To verify the conformance to agreed budget and time scales, -\item To prepare periodic progress reports in order to control the overall progress of the - project, -\item To organize the project meetings, -\item To set up a shared development infrastructure as a version control system and - development WEB site. -\end{itemize} -\end{objectif} -% -\begin{workpackage} - \subtask{Consortium agreement} This \ST consists in writing and ratifying the consortium agreement. - \begin{livrable} - \itemL{0}{6}{d}{\Smds}{Consortium agreement}{1:0:0} - A document describing the consortium agreement, signed by all the partners. - \end{livrable} - \subtask{Global management} This \ST concerns the global management of the deliverables and of the global - organization of the project at all the levels. - \begin{livrable} - \itemL{0}{36}{d}{\Smds}{Global project management}{1:1:1} - Global management of the project at all the - levels: progress monitoring, record keeping, meeting organization, review - organization, the writing of the review reports. - \end{livrable} - \subtask{Partner level management} This \ST consists in managing the project at the partner level. - It includes mainly the progress monitoring, the record keeping the participation to the - project meetings and the communication with the project leader and the other partners. - \begin{livrable} - \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5} Project management at the partner level. - \OtherPartner{0}{36}{\Supmc}{.5:.5:.5} - \OtherPartner{0}{36}{\Subs} {.5:.5:.5} - \OtherPartner{0}{36}{\Stima}{.5:.5:.5} - \OtherPartner{0}{36}{\Slip} {.5:.5:.5} - \end{livrable} - \subtask{Setup of dissemination infrastructure} - This \ST consists firstly in the building, and next in the administration and the - maintenance of the development and dissemination infrastructure. It is also in charge of - the COACH releases distribution. - \begin{livrable} - \itemV{0}{6}{x}{\Supmc}{Infrastructure development setup} - Setup of the development infrastructure - (version control system configuration, wiki). - \itemL{7}{36}{x}{\Supmc}{Infrastructure development}{1:.5:.5} - Standard management of a development - infrastructure (adding \& suppressing account, retrieving forgotten passwords, - creation and closing development branch, ...) - \end{livrable} -\end{workpackage} -% Index: r/task-1.tex =================================================================== --- /anr/task-1.tex (revision 290) +++ (revision ) @@ -1,179 +1,0 @@ -\begin{taskinfo} -\let\UPMC\leader -\let\ALL\enable -\end{taskinfo} -% -\begin{objectif} -The objectives of this task are the specification of the designer input, the -definition of the hardware architectural templates and of all the features -that the HAS tools will share. -An other objective is the specification of the framework used to facilitate the -exploitation and the integration of the core engine into an industrial flow. -\end{objectif} -% -\begin{workpackage} -\subtask{Specification of the COACH environment} - This \ST specifies the global COACH environment for the system designer: - the core engine which is seen as a black box associated - with a configuration framework based on Eclipse. - This framework will be integated into Magillem tool suite. - The deliverables specify - how to feed COACH (the inputs), - how to use COACH (use model), - what is generated (the outputs) - and how the Magillem framework iteracts with the core engine. - \begin{livrable} - \itemV{0}{6}{d}{\Supmc}{Use model specification} - This document describes the use model of COACH. It will be a cooperative work. - Its main parts are: - \begin{description} - \item[General overview] (\Supmc) - \item[CSG specification] (\Stima): - here the COACH System Generator Generator is specified: - how the task graph is described, the communication schemes and - its associated API (Application Programming Interface). - The base is the SRL library and the MWMR communication component defined - by the SocLib ANR project. - Nevertheless, these basic schemes will be enhanced to allow more efficient - synthesis. - \item[HAS specification] (\Subs): - this part focuses to the Hardware Accelerator Synthesis. - It specifies how tasks must be written (C/C++ subset) and how - communication schemes must be described for coprocessor synthesis. - \item[Magillem framework specification] (\Smds): - this part specifies the fonctionnalities enabling the interactions between - Magillem and the core engine. - \end{description} - \itemL{6}{12}{d}{\Supmc}{Use model specification}{3:0:0} - \setMacroInAuxFile{useModelSpecification} - The final version of the Use model specification enhanced - with the feed-backs of the demonstrator \STs. - \OtherPartner{0}{12}{\Slip} {2:0:0} - \OtherPartner{0}{12}{\Sirisa} {2:0:0} - \OtherPartner{0}{12}{\Stima} {3:0:0} - \OtherPartner{0}{12}{\Subs} {3:0:0} - \OtherPartner{0}{12}{\Sbull} {2:0:0} - \OtherPartner{0}{12}{\Sthales}{2:0:0} - \OtherPartner{0}{12}{\Smds} {2:0:0} -% \itemV{0}{6}{d}{\Supmc}{Use model specification} \setMacroInAuxFile{specGenManualI} -% The first version of the COACH specification. -% This document contains the general description of the framework, the use model and the -% description of the architectural templates. -% It refers to the HAS specification (deliverable {\specHasManual}) and -% to the CSG specifcation (deliverable \specCsgManual) for the COACH input -% descriptions. -% \itemL{6}{12}{d}{\Supmc}{COACH specification}{1:0:0} \setMacroInAuxFile{specGenManual} -% The final version of the {\specGenManualI} deliverable updated with the first -% feed-backs of the demonstrator \STs. -% \OtherPartner{0}{12}{\Sbull} {3:0:0} -% \OtherPartner{0}{12}{\Sthales}{1:0:0} -% \itemV{0}{6}{d}{\Stima}{CSG specification} \setMacroInAuxFile{specCsgManualI} -% The first version of the CSG (COACH System Generator) specification. -% It specifies how the task graph is described, the communication schemes and its -% associated API (Application Programming Interface). -% The base is the SRL library and the MWMR communication component defined by the SocLib -% ANR project. -% Nevertheless, these basic schemes will be enhanced to allow more efficient -% synthesis. -% \itemL{6}{12}{d}{\Stima}{CSG specification}{1:0:0} \setMacroInAuxFile{specCsgManual} -% The final version of the {\specGenManualI} deliverable updated with the first -% feed-backs of the demonstrator \STs. -% \itemV{0}{6}{d}{\Subs}{HAS specification} \setMacroInAuxFile{specHasManualI} -% The first version of the HAS (Hardware Accelerator Synthesis) specification. -% It specifies how tasks must be written (C/C++ subset) and how -% communication schemes defined in the {\specCsgManual} deliverable must be described for -% coprocessor synthesis. -% \itemL{6}{12}{d}{\Subs}{HAS specification}{2:0:0} \setMacroInAuxFile{specHasManual} -% The final version of the {\specGenManualI} deliverable updated with the first -% feed-backs of the demonstrator \STs. - \end{livrable} -\subtask{Internal software structure} - This \ST specifies the COACH software structure. The deliverable is a - document listing all the COACH software components and how they cooperate. - \begin{livrable} - \itemL{0}{6}{d}{\Supmc}{COACH internal \ganttlf software architecture}{1:0:0} - Description of the software list and the data flow among the tools. - \end{livrable} -\subtask{\xcoach format} - This \ST specifies the \xcoach and the \xcoachplus formats. - \begin{livrable} - \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification} - \setMacroInAuxFile{specXcoachDocI} - First release of the XML specification of the \xcoach format (DTD) - and its associated documentation allowing to start HLS tools development. - \itemV{6}{12}{d+x}{\Slip}{\xcoach format specification} - \setMacroInAuxFile{specXcoachDocII} - Second release of XML specification of the \xcoach format - taking into account the corrections and modifications that the - developers of HAS tools suggested. - \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{7:3:0} - \setMacroInAuxFile{specXcoachDoc} - Last release of XML specification of the \xcoach format enhanced with - the expression of loop potential parallelism. - \itemV{6}{12}{x}{\Subs}{First release of C2X} - \setMacroInAuxFile{specXcoachToCAI} - This delivrable groups 2 tools. - The first one C2X is a GCC plugin that generates a \xcoach description - (defined in {\specXcoachDocI} deliverable) from a C/C++ task description - (defined in {\specHasManual} deliverable). - The second one X2C regenerates a C description from a \xcoach - description. - % TACHE INCLUSE mais non decrite; Specification of the GCC driver tool. - \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0} - \setMacroInAuxFile{specXcoachToCA} - An updated version of C2X and X2C (\specXcoachToCAI) which supports the \xcoach format defined - in the {\specXcoachDoc} deliverable and the HAS input format defined in the {\specHasManual} - deliverable. -% \itemV{7}{12}{x}{\Subs}{First release of X2C} -% \setMacroInAuxFile{specXcoachToCBI} -% This second tool X2C regenerates a C description from a \xcoach -% description. -% \itemL{12}{18}{x}{\Subs}{X2C tool}{2:1:0} -% \setMacroInAuxFile{specXcoachToCB} -% The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined -% in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual} -% deliverable. - \itemV{12}{18}{x}{\Supmc}{First release of X2SC} - \setMacroInAuxFile{specXcoachToSystemCI} - The first release of the software tool X2SC that translates \xcoachplus description to CABA - and TLM-DT SystemC module. - \itemL{18}{24}{x}{\Supmc}{X2SC tool}{0:2:0} - \setMacroInAuxFile{specXcoachToSystemC} - Final release of the former software (\specXcoachToSystemCI). - \itemV{12}{18}{x}{\Subs}{First release of the X2VHDL} - \setMacroInAuxFile{specXcoachToVhdlI} - The first release of the software tool X2VHDL that translates \xcoachplus description to - synthesizable VHDL description. - \itemL{18}{24}{x}{\Subs}{X2VHDL tool}{0:3:0} - \setMacroInAuxFile{specXcoachToVhdl} - Final release of the former software (\specXcoachToVhdlI) and integration - of enhancements proposed in \novers{\specXilinxOptimization} deliverable. - \end{livrable} - -% TACHE INCLUSE SANS X2C & C2X -%\subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler. -% \begin{livrable} -% \itemL{0}{3}{d}{\Subs}{GCC driver specification}{1:0:0} -% Specification of the GCC driver tool. -% \itemV{3}{9}{x}{\Subs}{GCC driver} -% First release of the GCC driver tool. -% %en T0+18 car va peut etre evoluer en fonction du DSE µ-archi -% \itemL{9}{12}{x}{\Subs}{GCC driver}{3:0:0} -% Final release of the GCC driver tool. -% \end{livrable} - -\subtask{Tool for cell library creation} - Backend HLS tools use a characterized macro-cell library to build the - micro-architecture of a coprocessor. The characterisation of a cell depends - on the target device. The role of this \ST is to define the macro-cells and - to provite a tool that characterizes them automatically by synthesizing them - and by extracting their delays. This is done by using RTL synthesis. - \begin{livrable} - \itemL{0}{6}{d}{\Subs}{Macro-cell definition}{1:0:0} - \setMacroInAuxFile{specMacroCell} - Definition of the macro cells and the file format describing them. - \itemL{6}{12}{x}{\Subs}{Macro-cell library generator}{2:0:0} - Final release of the software tool that generates automatically the characterized macro-cell library - for a FPGA device. - \end{livrable} -\end{workpackage} Index: r/task-2.tex =================================================================== --- /anr/task-2.tex (revision 290) +++ (revision ) @@ -1,76 +1,0 @@ -\begin{taskinfo} -\let\UPMC\leader -\let\IRISA\enable -\let\TIMA\enable -\let\XILINX\enable -\let\UBS\enable -\end{taskinfo} -% -\begin{objectif} -This task deals with the prototyping and the generation of FPGA-SoC digital systems. -Its is described on figure~\ref{archi-csg}. -Its objective is to allow the system designer to explore the design space by -quickly prototyping and then to automatically generate the FPGA-SoC systems. -This task consists of: -\begin{itemize} -\item The development of the synthesizable models required for the connection of -the coprocessors on the platform bus (2 bridges). -\item The configuration and the development of drivers of the operating systems (Board Support Package, HAL), -\item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system -including its bitstream and software executable code, -\end{itemize} -A first release will be delivered at $T0+12$ to allow the demonstrators to start working. -This release will include the standard communication schemes based on SoCLib MWMR component -and support the neutral architectural template for prototyping and hardware generation. -\end{objectif} -% -\begin{workpackage} -\subtask{Bridge implementation} - This \ST deals with the development of the synthesizable models required for the connection of - the coprocessors on the platform bus). - \begin{livrable} - \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} - \setMacroInAuxFile{hpcPlbBridge} - The synthesizable VHDL description of a PLB/VCI bridge. - \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} - \setMacroInAuxFile{hpcAvalonBridge} - The synthesizable VHDL description of an AVALON/VCI bridge. - \end{livrable} -\subtask{OS setup} This \ST consists of the configuration of the SocLib DNA operating - system and the development of drivers for the hardware architectural templates. - For the \altera and \xilinx architectural templates, the OSs must also be ported on - the NIOS2 and MICROBLAZE processors. - \begin{livrable} -%IVG \itemV{6}{8}{x}{\Supmc}{MUTEKH OS} -%IVG The drivers required for the first CSG milestone (deliverable \csgCoachArch). -%IVG \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers} -%IVG The drivers required for the second CSG milestone ({\csgPrototypingOnly}). -%IVG \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2} -%IVG Final release of the MUTEKH OS drivers. -%IVG \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0} -%IVG Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors. - \itemV{6}{8}{x}{\Stima}{DNA OS} - The drivers required for the first CSG milestone. - \itemV{8}{18}{x}{\Stima}{DNA 0S} - The drivers required for the second CSG milestone. - \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2} - Final release of the DNA OS drivers. - \itemL{6}{18}{x}{\Stima}{Porting of DNA OS}{3:1:0} - Porting of DNA OS on the NIOS2 and MICROBLAZE processors. - \end{livrable} -% -\subtask{Implementation of CSG} This \ST corresponds to the COACH System Generator (CSG) software. - \begin{livrable} - \itemV{0}{12}{x}{\Supmc}{CSG tool} - The first software release of the CSG tool that will allow demonstrators to start - working by using the neutral architectural template only for SystemC. - \itemV{12}{18}{x}{\Supmc}{CSG} - The second release of CSG integrates the VHDL driver for the neutral - architectural template, and an integration of an HLS tools - but only for SystemC prototyping. - \itemV{18}{24}{x}{\Supmc}{CSG} - This release extends CSG to FPGA-SoC generation for the \xilinx and \altera architectural template. - \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} \setMacroInAuxFile{csgImplementation} - Final release of CSG enhanced by the demonstrator's feedback. - \end{livrable} -\end{workpackage} Index: r/task-3.tex =================================================================== --- /anr/task-3.tex (revision 290) +++ (revision ) @@ -1,83 +1,0 @@ -\begin{taskinfo} -\let\LIP\leader -\let\IRISA\enable -\let\UBS\enable -\let\UPMC\enable -\let\TIMA\enable -\end{taskinfo} -% -\begin{objectif} -The objective of this task is to convert the input specification of -an hardware accelerator, which must be written in a familiar language -(C/C++) with as few constraints as possible, into a form suitable for -the HLS tools (i.e. HAS back-end tools of the COACH project). If the -target is an ASIP, the frontend has to extract -patterns from the source code and convert them into the definition -of an extensible processor. If the target is a process network, the -front end has to distribute the workload and the data sets as fairly -as possible, identify communication channels, and output an \xcoach -description. -\end{objectif} -% -\begin{workpackage} - \subtask{ASIP compiler} - This sub-task aims at providing compiler support for custom instructions - within the HAS front-end. It will take as input the COACH intermediate - representation, and will output an annotated COACH IR containing the custom - instructions definitions along with their occurrence in the application. - \begin{livrable} - \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow} - In this first version of the software, the computations patterns corresponding to - custom instructions are specified by the user, and then automatically extracted (when - beneficial) from the application intermediate representation. - \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0} - In this second version, the software will also be able to automatically identify - interesting pattern candidates in the application code, and use them as custom - instructions. - \end{livrable} - - \subtask{Micro-architectural template models for ASIP} - In this sub-task, we provide micro-architectural template models for the two target - processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. - For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) - of the architecture, along with its architectural extensions - \begin{livrable} - \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS } - { A SystemC simulation model for a simple extensible MIPS architectural template } - \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0} - {A SystemC simulation model for an extensible MIPS with a tight architectural integration of - its instruction set extensions} - \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS} - {A synthesizable VHDL model for a simple extensible MIPS architectural template} - \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0} - {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of - its instruction set extensions} - \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2} - {An evaluation report with quantitative analysis of the performance/area trade-off induced by - the different approaches} - \end{livrable} - - \subtask{Parallelism optimization} - Extraction of parallelism in polyhedral loops and conversion into a process network. - \begin{livrable} - \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition} - Description and specification of a process construction method for programs with - polyhedral loops. - \itemL{30}{36}{d}{\Slip}{Process generation method}{10:0:9} - Final assessment of the method and improved version of the specification. - \itemV{6}{12}{x}{\Slip}{Process construction} - Preliminary implementation in the Syntol framework. - At this step the software will just implement a single constructor. - \itemV{12}{18}{x}{\Slip} {Arrays and FIFO} - Implementation of the array contraction and FIFO construction algorithm. - Conversion of the input and output to the \xcoach format. - \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension} - Extension of automatic parallelization and array contraction - to non-polyhedral loops. Implementation in the Bee framework. - \itemL{30}{36}{x}{\Slip} {Process/FIFO construction}{10:20:12} - Final release taking into account the feedbacks from the - demonstrator \STs. - \end{livrable} - -\end{workpackage} - Index: r/task-4.tex =================================================================== --- /anr/task-4.tex (revision 290) +++ (revision ) @@ -1,73 +1,0 @@ -\begin{taskinfo} -\let\UBS\leader -\let\UPMC\enable -\let\TIMA\enable -\let\XILINX\enable -\end{taskinfo} -% -\begin{objectif} -The objectives of this task are to provide the two HAS back-ends of the COACH project and -a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required -by the processors and the system bus. -\\ -The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an -\xcoachplus description, i.e. an \xcoach description annotated with hardware information such as -variables binding to registers, operations bindings to cells/fonctional units, operation scheduling... -The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable and the \xcoachplus being treated by -the \novers{\specXcoachToSystemC} and the \novers{\specXcoachToVhdl} deliverables, -this task strongly depends on task~1. -\par -For the two HAS front-end, this task is based on the already existing HLS tools GAUT and -UGH. These tools are complementary and not in competition because they cover respectively -data and control dominated designs. -\end{objectif} - -\begin{workpackage} -\subtask{Making HAS back-end to read \xcoach format} - The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. - by implementing the mechanism to read \xcoach format. - \begin{livrable} - \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0} - Release of the UGH software that reads \xcoach format. - \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0} - Release of the GAUT software that is able to read \xcoach format. - \end{livrable} -% -\subtask{Making HAS back-end to write \xcoachplus format} - The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. - by implementing the mechanism to write \xcoachplus format. - \begin{livrable} - \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0} - Release of the UGH software that writes \xcoachplus format. - \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0} - Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format. - \end{livrable} -% -\subtask{Adapting HAS tools to the COACH communication schemes} - \begin{livrable} - \itemL{12}{18}{x}{\Supmc}{UGH update for COACH communications}{0:2:4.0} - Release of the UGH software that interprets the API of task communication. - \itemL{12}{18}{x}{\Subs}{GAUT update for COACH communications}{0:2:4.0} - Release of the GAUT software that interprets the API of task communication. - \end{livrable} - -\subtask{Coprocessor frequency adaptation} - In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors - generated by HLS synthesis must respect this frequency. However, the HLS tools can not - guarantee that the micro-architectures they generate accurately respect this - frequency. This is especially the case when the target is a FPGA device, because the - delays are really known only after the RTL synthesis and that estimated delays used - by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts - the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL - synthesis. - \begin{livrable} - \itemV{0}{12}{d}{\Supmc}{Frequency calibration} - A document describing the set up of the coprocessor frequency calibration. - \itemV{12}{24}{x}{\Supmc}{Frequency calibration} - \setMacroInAuxFile{freqCalibrationVhdl} - A VHDL description of hardware added to the coprocessor to enable the calibration. - \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5} - The frequency calibration software consists of a driver in the FPGA-SoC operating - system and of a control software. - \end{livrable} -\end{workpackage} Index: r/task-5.tex =================================================================== --- /anr/task-5.tex (revision 290) +++ (revision ) @@ -1,107 +1,0 @@ -% vim:set spell: -% vim:spell spelllang=en: - -\begin{taskinfo} -\let\BULL\leader -\let\UPMC\enable -\let\TIMA\enable -\let\THALES\enable -\let\XILINX\enable -\end{taskinfo} -% -\begin{objectif} -This task deals with the COACH HPC feature that consists in accelerating an existing -application running on a PC by migrating critical parts into a SoC implemented on an -FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}). -It consists in: -\begin{itemize} -\item Specification and implementation of the communication schemes between the software part running on the PC and the -FPGA-SoC. -\item Providing a performance analysis tool helping user in the HPC partitionning (figure~\ref{archi-hpc}). -\item Providing support for configuration of the FPGA in order to set up the HPC environement. -\end{itemize} - -The low level hardware transmission support will be the PCI/X bus which allows high bit-rate -transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for -their FPGA and that GPU HPC softwares use also it. -%This will allow us at least to be inspired by GPU communication schemes and may be to reuse -%parts of the GPU softwares. - -\end{objectif} -% -\begin{workpackage} - \subtask{Implementation of API between PC and FPGA-SoC} - \begin{livrable} - \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} - \setMacroInAuxFile{hpcCommApi} - Specification describing the API. - \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} - \setMacroInAuxFile{hpcCommHelper} - A library implementing the communication API defined in the {\hpcCommApi} deliverable. - This library is dedicated to help the end-user to partition an application for HPC. - \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0} - \setMacroInAuxFile{hpcCommLinux} - The PC part of the HPC communication API that communicates with the FPGA-SOC, a - library and a LINUX module. -% \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0} -% \setMacroInAuxFile{hpcMutekDriver} -% The FPGA-SoC part of the communication API, a driver. - \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} - \setMacroInAuxFile{hpcDnaDriver} - The FPGA-SoC part of the communication API. -% Port of the {\hpcMutekDriver} driver on the DNA OS. -% \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} -% Bug corrections and enhancements of communication middleware -% (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux}, -% \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}). - \end{livrable} - -\subtask{SystemC model of the PCI/X} - This \ST deals with the implementation of SystemC modules - required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. - \begin{livrable} -% FIXME: moved to task 3 (CSG) -% \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} -% \setMacroInAuxFile{hpcPlbBridge} -% The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. -% \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} -% \setMacroInAuxFile{hpcAvalonBridge} -% The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. - \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} - The SystemC description of a component that generates PCI/X traffic. It is - required to prototype FPGA-SoC dedicated to HPC. - \end{livrable} - -\subtask{HPC environment set up} - -% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. - \begin{livrable} - \itemL{24}{36}{x}{\Stima}{Support for HPC environment set up}{0:0:2} - Modification of the CSG software to set-up the HPC environement: Bitsream loader. - \end{livrable} -% \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} -% This livrable is a CSG module allowing to partition the task graph along -% the dynamic partial reconfiguration regions. The resulting task-region assignement -% is directly used for generation of bitstreams. The module also produces reconfiguration -% management software to be run on the SoC-FPGA. -% \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3} -% \setMacroInAuxFile{hpcDynconfDriver} -% The drivers required by the DNA OS in order to manage dynamic partial -% reconfiguration inside the SoC-FPGA. -% \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for MUTEKH drivers}{0:0:1} -% Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. -% \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} -% Extension of the HPC partionning helper in order to integrate dynamic partial -% reconfiguration dedicated features (reconfiguration time of regions, variable -% number of coprocessors). -% \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2} -% \xilinx will work with \tima in order to better take into account during -% partitioning decisions specific constraints due to partial reconfiguration process. -% The deliverable is a document describing the \xilinx specific constraints. -% \end{livrable} -% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board -% % with its PCI/X IP. These boards are dedicated to the COACH HPC development. -% % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. -% % \begin{livrable} -% % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. -\end{workpackage} Index: r/task-6.tex =================================================================== --- /anr/task-6.tex (revision 290) +++ (revision ) @@ -1,100 +1,0 @@ -\begin{taskinfo} -\let\BULL\enable -\let\THALES\leader -\let\NAVTEL\enable -\let\ZIED\enable -\end{taskinfo} -% -\begin{objectif} -This task groups the demonstrators of the COACH project. -The demonstrators cover various domains and application types to drive -the specification choices and to check most of the COACH features. -\end{objectif} -% -\begin{workpackage} - \subtask{\bull HPC demonstrator} - The application that \bull proposes is HPC oriented. - The domain of the application is the treatment of medical images (image noise - reduction and segmentation or registration). - Our expectation from COACH project is to enhance the \bull HPC solutions that - are currently based on multi-cores and GPUs with fine grain parallelism on FPGA. - \begin{livrable} - \itemV{0}{6}{d}{\Sbull}{\bull demonstrator} - The deliverable is a document that describes the application that will be use as - demonstrator. - \itemV{6}{12}{x}{\Sbull}{\bull demonstrator} - The deliverable is the specification of the demonstrator in COACH input format - defined in the \novers{\useModelSpecification} deliverable. - \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{2:6:10} - Validation of the demonstrator, the deliverable is a document - describing the result of the experimentations. - \end{livrable} - - \subtask{\TRT Embedded SoC demonstrator} - The objective of this sub-task is to specify the \TRT application and to develop the - high level code. This application is in the domain of surveillance of critical - infrastructures. The objective is to detect and classify the presence of humans in the - restricted area. The algorithm is based on the work of Viola and - Jones~\cite{thales-viola}. It implements in particular a cascade of classifiers - operating on Haar like features, where simple weak classifiers at the beginning of the - cascade reject a majority of void sub-windows, before more complex classifiers - concentrate on potential regions of interest. This application is computation - intensive and also makes an intensive use of binary decision trees to cascade the - filters, which makes it a good candidate to assess the COACH platform. - \\ - Moreover, the higher levels of computing can involve tracking and data fusion between - several camera streams and some other informations. - The targeted system will be composed of one camera connected to a PC. - All the computing part of the application is executed on a FPGA board connected to the - PC. - \begin{livrable} - \itemV{0}{6}{d}{\Sthales}{\thales demonstrator (step 1)} - \setMacroInAuxFile{trtAppSpecification} - This deliverable is a document that specifies the application. - \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0} - This deliverable is the code of the application specified former - deliverable (\trtAppSpecification). - \end{livrable} - - \subtask{SPEAR-DE adaptation for COACH} - \TRT will use its internal software environment tool SPEAR DE to describe the - application. The tool is able to partition and to generate the code for the target. \\ - In this task, we will adapt SPEAR DE to generate the application description input of - COACH framework. We will also describe the three templates of architecture in order to - be able to partition the application on the architecture. - \begin{livrable} - \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:7:0} - \setMacroInAuxFile{trtSpearde} - Adaptation of SPEAR-DE for COACH framework. - \end{livrable} - - \subtask{\mds use case} - \mds will use ................. - \begin{livrable} - \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0} - \setMacroInAuxFile{trtSpearde} - Adaptation of SPEAR-DE for COACH framework. - \end{livrable} - - \subtask{Evaluation report} - % FIXME: AJOUTER une evaluation de BULL ET MDS - In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify - its ability to generate a whole VHDL of an embedded system on FPGA for an application - mixing control and data flow aspects. \TRT will evaluate the performance of the - generated system in terms of GOPS, and the design time from a high level description. - \begin{livrable} - \itemV{18}{24}{d+x}{\Sthales}{\thales demonstrator (step 2)} - This deliverable is a document describing the result got for the application - (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18. - The updated code of the application will be also provide. - \itemV{24}{30}{d+x}{\Sthales}{\thales demonstrator (step 2)} - This deliverable is a document describing the result got for the application - (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24. - The updated code of the application will be also provide. - \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:5:5} - This deliverable is a document that validates and evaluates COACH (final release) - for the \thales demonstrators (\trtAppSpecification). - The updated code of the application will be also provide. - \end{livrable} - -\end{workpackage} Index: r/task-7.tex =================================================================== --- /anr/task-7.tex (revision 290) +++ (revision ) @@ -1,75 +1,0 @@ -\begin{taskinfo} -\let\MDS\leader -\let\ALL\enable -\end{taskinfo} -% -\begin{objectif} -This task relates to the diffusion of the project results. -The objective is to ensure the COACH dissemination by publishing on a public WEB site all -the information that a COACH user requires. -The main information features are: -\begin{itemize} -\item The COACH releases (milestones and final release) and their associated installation manuals. -\item The COACH user reference manual. -\item The user manual of the various tools. -\item A COACH tutorial. -\item The conference publication. -\item A user wiki. -\end{itemize} -\end{objectif} -% -\begin{workpackage} - \subtask{Distribution of COACH releases} - \begin{livrable} - \itemL{6}{36}{d+x}{\Supmc}{Open source release}{1:.5:.5} - \OtherPartner{12}{36}{\Stima}{0:2:1} - This deliverable deals with the elaboration of the COACH software milestones and - final releases with their installation manuals and to publish then into the WEB - site. - \itemL{6}{36}{d+x}{\Smds}{Commercial release}{1:.5:.5} - This deliverable deals with the elaboration of a release of COACH integrated - into the Magillem environment. - \end{livrable} - \subtask{Tutorial} - \label{subtask-tutorial} - This \ST consists of making a COACH tutorial and to publish it on the public WEB - site. The tutorial example will also be used as reference demonstrator of the - framework. - The application of this tutorial will be a Motion JPEG application. - \begin{livrable} - \itemV{0}{6}{x}{\Supmc}{Tutorial specification} - Choice of the application and its implementation as a C/C++ program. - \itemV{6}{12}{d+x}{\Supmc}{Tutorial} - The application is split into two communicating parts, the PC part and FPGA-SoC part. - By using the features the T0+12 milestone provides, - the tutorial describes how this efficient partionning was obtained. - The FPGA-SoC part is described as communicating task graph. The tutorial also describes - how a promising task graph can be obtained. - \itemV{18}{24}{d}{\Supmc}{Tutorial} - \OtherPartner{12}{36}{\Smds}{0:2:2} - This tutorial shows how a task can be migrated to coprocessor using HAS tools and - how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and - architectural template available in T0+24 milestone.\par - A part (written by \Smds) will be dedicated to the integration of COACH generated IP - into an IP-XACT based design flow (such as SOCKET). - \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1} - The final release of the tutorial. - \end{livrable} - \subtask{Reference user manuals} - This \ST consists of making the COACH user reference manuals. - They will be published on the public WEB site. - \begin{livrable} - \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:1:0} - This user manual shows how to generate a complete HW/SW system by using CSG tool. - \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:1:0} - This user manual shows how to apply loop transformations to a task. - \itemL{18}{36}{d}{\Sirisa}{ASIP user manual}{0:1:1} - This user manual shows how to customize a processor to obtain an ASIP. - \itemL{18}{24}{d}{\Subs}{HLS user manual}{0:1:0} - This user manual shows how a task can be synthesized by using HLS tools developped in - the COACH project. - \OtherPartner{12}{36}{\Subs}{0:2:2} - \itemL{18}{36}{d}{\Smds}{Magillem framework user manual}{0:1:1} - This user manual describes how to use COACH within the IP-XACT based Magillem tool suite. - \end{livrable} -\end{workpackage} Index: /anr/task-backbone.tex =================================================================== --- /anr/task-backbone.tex (revision 291) +++ /anr/task-backbone.tex (revision 291) @@ -0,0 +1,124 @@ +\begin{taskinfo} +\let\UPMC\leader +\let\ALL\enable +\end{taskinfo} +% +\begin{objectif} +The objectives of this task are the specification of the designer input, the +definition of the hardware architectural templates and of all the features +that the HAS tools will share. +An other objective is the specification of the framework used to facilitate the +exploitation and the integration of the core engine into an industrial flow. +\end{objectif} +% +\begin{workpackage} +\subtask{Specification of the COACH environment} + This \ST specifies the global COACH environment for the system designer: + the core engine which is seen as a black box associated + with a configuration framework based on Eclipse. + This framework will be integrated into Magillem tool suite. + The deliverables specify + how to feed COACH (the inputs), + how to use COACH (use model), + what is generated (the outputs) + and how the Magillem framework interacts with the core engine. + \begin{livrable} + \itemV{0}{6}{d}{\Supmc}{Use model specification} + This document describes the use model of COACH. It will be a cooperative work. + Its main parts are: + \begin{description} + \item[General overview] (\Supmc) + \item[CSG specification] (\Stima): + here the COACH System Generator is specified: + how the task graph is described, the communication schemes and + its associated API (Application Programming Interface). + The base is the SRL library and the MWMR communication component defined + by the SocLib ANR project. + Nevertheless, these basic schemes will be enhanced to allow more efficient + synthesis. + \item[HAS specification] (\Subs): + this part focuses to the Hardware Accelerator Synthesis. + It specifies how tasks must be written (C/C++ subset) and how + communication schemes must be described for coprocessor synthesis. + \item[Magillem framework specification] (\Smds): + this part specifies the functionalities enabling the interactions between + Magillem and the core engine. + \end{description} + \itemL{6}{12}{d}{\Supmc}{Use model specification}{3:0:0} + \setMacroInAuxFile{useModelSpecification} + The final version of the Use model specification enhanced + with the feed-backs of the demonstrator \STs. + \OtherPartner{0}{12}{\Slip} {2:0:0} + \OtherPartner{0}{12}{\Sirisa} {2:0:0} + \OtherPartner{0}{12}{\Stima} {3:0:0} + \OtherPartner{0}{12}{\Subs} {3:0:0} + \OtherPartner{0}{12}{\Sbull} {2:0:0} + \OtherPartner{0}{12}{\Sthales}{2:0:0} + \OtherPartner{0}{12}{\Smds} {2:0:0} + \end{livrable} +% +\subtask{Internal software structure} + \begin{livrable} + \itemL{0}{6}{d}{\Supmc}{COACH internal \ganttlf software architecture}{1:0:0} + This document lists all the COACH software components and how they cooperate. + \end{livrable} +% +\subtask{\xcoach format} + This \ST specifies the \xcoach and the \xcoachplus formats. + \begin{livrable} + \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification} + \setMacroInAuxFile{specXcoachDocI} + First release of the XML specification of the \xcoach format (DTD) + and its associated documentation allowing to start HLS tools development. + \itemV{6}{12}{d+x}{\Slip}{\xcoach format specification} + \setMacroInAuxFile{specXcoachDocII} + Second release of XML specification of the \xcoach format + taking into account the corrections and modifications that the + developers of HAS tools suggested. + \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{7:3:0} + \setMacroInAuxFile{specXcoachDoc} + Last release of XML specification of the \xcoach format enhanced with + the expression of loop potential parallelism. +% + \itemV{6}{12}{x}{\Subs}{C2X tool} + \setMacroInAuxFile{specXcoachToCAI} + This deliverable groups 2 tools. + The first one C2X is a GCC plugin that generates a \xcoach description + (defined in {\specXcoachDocI} deliverable) from a C/C++ task description. + The second one X2C regenerates a C description from a \xcoach description. + \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0} + \setMacroInAuxFile{specXcoachToCA} + An updated version of C2X and X2C (\specXcoachToCAI) which supports the + \xcoach format defined in the {\specXcoachDoc} deliverable. +% + \itemV{12}{18}{x}{\Supmc}{First release of X2SC} + \setMacroInAuxFile{specXcoachToSystemCI} + The first release of the software tool X2SC that translates \xcoachplus + description to CABA and TLM-DT SystemC module. + \itemL{18}{24}{x}{\Supmc}{X2SC tool}{0:2:0} + \setMacroInAuxFile{specXcoachToSystemC} + Final release of the former software (\specXcoachToSystemCI). + \itemV{12}{18}{x}{\Subs}{First release of the X2VHDL} + \setMacroInAuxFile{specXcoachToVhdlI} + The first release of the software tool X2VHDL that translates \xcoachplus + description to synthesizable VHDL description. + \itemL{18}{24}{x}{\Subs}{X2VHDL tool}{0:3:0} + \setMacroInAuxFile{specXcoachToVhdl} + Final release of the former software (\specXcoachToVhdlI). + \end{livrable} +% +\subtask{Tool for cell library creation} + Back-end HLS tools use a characterized macro-cell library to build the + micro-architecture of a coprocessor. The characterization of a cell depends + on the target device. The role of this \ST is to define the macro-cells and + to provide a tool that characterizes them automatically by synthesizing them + and by extracting their delays. This is done by using RTL synthesis. + \begin{livrable} + \itemL{0}{6}{d}{\Subs}{Macro-cell definition}{1:0:0} + \setMacroInAuxFile{specMacroCell} + Definition of the macro cells and the file format describing them. + \itemL{6}{12}{x}{\Subs}{Macro-cell library generator}{2:0:0} + Final release of the software tool that generates automatically the + characterized macro-cell library for a FPGA device. + \end{livrable} +\end{workpackage} Index: /anr/task-backend.tex =================================================================== --- /anr/task-backend.tex (revision 291) +++ /anr/task-backend.tex (revision 291) @@ -0,0 +1,118 @@ +\begin{taskinfo} +\let\UBS\leader +\let\UPMC\enable +\let\TIMA\enable +\end{taskinfo} +% +\begin{objectif} +The objectives of this task are to provide two HAS back-ends and +a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required +by the processors and the system bus. +\\ +The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach +description and provides an \xcoachplus description (a \xcoach description +annotated with hardware information such as variables binding to registers, +operations bindings to cells/functional units). +%The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable +%and the \xcoachplus being treated by the \novers{\specXcoachToSystemC} and the +%\novers{\specXcoachToVhdl} deliverables, this task strongly depends on task~1. +\par +For the two HAS front-end, this task is based on the already existing HLS tools GAUT and +UGH. These tools \textbf{are complementary and not in competition} because they +cover respectively data and control dominated designs. +\end{objectif} + +\begin{workpackage} +\subtask{Integration of UGH \& GAUT HLS tools to COACH} + This adaptation will be done incrementally in three steps: + \begin{enumerate} + \item Make tools to read \xcoach format defined in \novers{\specXcoachDoc} deliverable. + \item Make tools to recognize the API of task communication defined in + \novers{\useModelSpecification} deliverable. + \item Make tools to write \xcoachplus format to let + \novers{\specXcoachToSystemC} deliverable generate the SystemC model and + \novers{\specXcoachToVhdl} deliverable generate the synthesizable VHDL description. + \end{enumerate} + \begin{livrable} + \itemV{6}{12}{x}{\Stima}{UGH integration} + UGH release that reads \xcoach format. + \itemV{12}{18}{x}{\Stima}{UGH integration} + UGH release that interprets the task communication API. + \itemV{18}{24}{x}{\Supmc}{UGH integration} + UGH release that writes \xcoachplus format. + \itemL{24}{36}{x}{\Stima}{UGH integration}{12:4:3} + \OtherPartner{0}{12}{\Supmc}{1:6:3} + UGH release taking into account demonstrator's feedback. +% + \itemV{6}{12}{x}{\Subs}{GAUT integration} + GAUT release that reads \xcoach format. + \itemV{12}{18}{x}{\Subs}{GAUT integration} + GAUT release that interprets the task communication API. + \itemV{18}{24}{x}{\Subs}{GAUT integration} + GAUT release that writes \xcoachplus format. + \itemL{24}{36}{x}{\Subs}{GAUT integration}{6:6:3} + \setMacroInAuxFile{gautFinal} + GAUT release taking into account demonstrator's feedback. + \end{livrable} +% +\subtask{Coprocessor frequency adaptation} + In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors + generated by HLS synthesis must respect this frequency. However, the HLS tools can not + guarantee that the micro-architectures they generate accurately respect this + frequency. This is especially the case when the target is a FPGA device, because the + delays are really known only after the RTL synthesis and that estimated delays used + by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts + the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL + synthesis. + \begin{livrable} + \itemV{0}{12}{d}{\Supmc}{Frequency calibration} + A document describing the set up of the coprocessor frequency calibration. + \itemV{12}{24}{x}{\Supmc}{Frequency calibration} + A VHDL description of hardware added to the coprocessor to enable the calibration. + \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5} + \setMacroInAuxFile{freqCalibrationVhdl} + The frequency calibration software consists of a driver in the FPGA-SoC operating + system and of a control software. + \end{livrable} +% +\subtask{GAUT enhancement} + \begin{livrable} + \itemV{18}{24}{d}{\Subs}{GAUT enhancement} + Specification of GAUT enhancements. + The first ones is to support new constraints and objectives. + The second one is a Design Space Exploration framework, GAUT will be + able to use synthesis feed-back informations in order to explore the + design space and to generate optimized architectures. + \itemL{24}{36}{x}{\Subs}{GAUT enhancement}{0:4:4} + Integration of these enhancements into the final GAUT release + ({\gautFinal} deliverable). + \end{livrable} +\end{workpackage} +%% +%% \subtask{Making HAS back-end to read \xcoach format} +%% The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. +%% by implementing the mechanism to read \xcoach format. +%% \begin{livrable} +%% \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0} +%% Release of the UGH software that reads \xcoach format. +%% \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0} +%% Release of the GAUT software that is able to read \xcoach format. +%% \end{livrable} +%% % +%% \subtask{Making HAS back-end to write \xcoachplus format} +%% The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. +%% by implementing the mechanism to write \xcoachplus format. +%% \begin{livrable} +%% \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0} +%% Release of the UGH software that writes \xcoachplus format. +%% \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0} +%% Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format. +%% \end{livrable} +%% % +%% \subtask{Adapting HAS tools to the COACH communication schemes} +%% \begin{livrable} +%% \itemL{12}{18}{x}{\Supmc}{UGH update for COACH communications}{0:2:4.0} +%% Release of the UGH software that interprets the API of task communication. +%% \itemL{12}{18}{x}{\Subs}{GAUT update for COACH communications}{0:2:4.0} +%% Release of the GAUT software that interprets the API of task communication. +%% \end{livrable} Index: /anr/task-csg.tex =================================================================== --- /anr/task-csg.tex (revision 291) +++ /anr/task-csg.tex (revision 291) @@ -0,0 +1,66 @@ +\begin{taskinfo} +\let\UPMC\leader +\let\TIMA\enable +\end{taskinfo} +% +\begin{objectif} +The objectives of this task are to allow the system designer to explore the +design space by quickly prototyping and then to automatically generate the +FPGA-SoC systems. It is described on figure~\ref{archi-csg} and it consists of: +\begin{itemize} + \item The development of the synthesizable models required for the connection + of the coprocessors on the platform bus (2 bridges). + \item The configuration and the development of drivers of the operating + systems (Board Support Package, HAL). + \item The CSG software that generates the SystemC simulators for prototyping + and the FPGA-SoC system including its bitstream and software executable code. +\end{itemize} +A first release will be delivered at $T0+12$ to allow the demonstrators to start working. +This release will include the standard communication schemes based on SoCLib MWMR component +and support the neutral architectural template for prototyping and hardware generation. +\end{objectif} +% +\begin{workpackage} +\subtask{Bridge implementation} + This \ST deals with the development of the synthesizable models required for + the connection of the coprocessors on the platform bus. + \begin{livrable} + \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} + \setMacroInAuxFile{hpcPlbBridge} + The synthesizable VHDL description of a PLB/VCI bridge. + \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} + \setMacroInAuxFile{hpcAvalonBridge} + The synthesizable VHDL description of an AVALON/VCI bridge. + \end{livrable} +\subtask{OS setup} + This \ST consists of the configuration of the SocLib DNA operating + system and the development of drivers for the hardware architectural templates. + For the \altera and \xilinx architectural templates, the OS must also be ported on + the NIOS2 and MICROBLAZE processors. + \begin{livrable} + \itemV{6}{8}{x}{\Stima}{DNA OS} + The drivers required for the first CSG milestone. + \itemV{8}{18}{x}{\Stima}{DNA 0S} + The drivers required for the second CSG milestone. + \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2} + Final release of the DNA OS drivers. + \itemL{6}{18}{x}{\Stima}{Ports of DNA OS}{3:1:0} + Porting of DNA OS on the NIOS2 and MICROBLAZE processors. + \end{livrable} +\subtask{Implementation of CSG} + \begin{livrable} + \itemV{0}{12}{x}{\Supmc}{CSG tool} + The first software release of the CSG tool that will allow demonstrators to start + working by using the neutral architectural template only for SystemC. + \itemV{12}{18}{x}{\Supmc}{CSG} + The second release of CSG integrates the VHDL driver for the neutral + architectural template, and an integration of an HLS tools + but only for SystemC prototyping. + \itemV{18}{24}{x}{\Supmc}{CSG} + This release extends CSG to FPGA-SoC generation for the \xilinx and + \altera architectural template. + \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} + \setMacroInAuxFile{csgImplementation} + Final release of CSG enhanced by the demonstrator's feedback. + \end{livrable} +\end{workpackage} Index: /anr/task-demonstrator.tex =================================================================== --- /anr/task-demonstrator.tex (revision 291) +++ /anr/task-demonstrator.tex (revision 291) @@ -0,0 +1,116 @@ +\begin{taskinfo} +\let\MDS\enable +\let\BULL\enable +\let\THALES\leader +\end{taskinfo} +% +\begin{objectif} +This task groups the demonstrators of the COACH project. +The demonstrators cover various domains and application types to drive +the specification choices and to check most of the COACH features. +\end{objectif} +% +\begin{workpackage} +% +\subtask{\bull HPC demonstrator} + The application that \bull proposes is HPC oriented. + The domain of the application is the treatment of medical images (image noise + reduction and segmentation or registration). + Our expectation from COACH project is to enhance the \bull HPC solutions that + are currently based on multi-cores and GPUs with fine grain parallelism on FPGA. + \begin{livrable} + \itemV{0}{6}{d}{\Sbull}{\bull demonstrator} + The deliverable is a document that describes the application that will be use as + demonstrator. + \itemV{6}{12}{x}{\Sbull}{\bull demonstrator} + The deliverable is the specification of the demonstrator in COACH input format + defined in the \novers{\useModelSpecification} deliverable. + \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{2:6:10} + \setMacroInAuxFile{bullAppSpecification} + Validation of the demonstrator, the deliverable is a document + describing the result of the experimentations. + \end{livrable} +% +\subtask{\thales Embedded SoC demonstrator} + The objective of this sub-task is to specify the \thales application and to develop the + high level code. This application is in the domain of surveillance of critical + infrastructures. The objective is to detect and classify the presence of humans in the + restricted area. The algorithm is based on the work of Viola and + Jones~\cite{thales-viola}. It implements in particular a cascade of classifiers + operating on Haar like features, where simple weak classifiers at the beginning of the + cascade reject a majority of void sub-windows, before more complex classifiers + concentrate on potential regions of interest. This application is computation + intensive and also makes an intensive use of binary decision trees to cascade the + filters, which makes it a good candidate to assess the COACH platform. + \\ + Moreover, the higher levels of computing can involve tracking and data fusion between + several camera streams and some other informations. + The targeted system will be composed of one camera connected to a PC. + All the computing part of the application is executed on a FPGA board connected to the + PC. + \begin{livrable} + \itemV{0}{6}{d}{\Sthales}{\thales demonstrator} + \setMacroInAuxFile{trtAppSpecification} + This deliverable is a document that specifies the application. + \itemL{6}{12}{x}{\Sthales}{\thales demonstrator}{4:0:0} + This deliverable is the code of the application specified former + deliverable (\trtAppSpecification). + \end{livrable} +% +\subtask{SPEAR-DE adaptation for COACH} + \thales will use its internal software environment tool SPEAR DE to describe the + application. The tool is able to partition and to generate the code for the target. \\ + In this task, we will adapt SPEAR DE to generate the application description input of + COACH framework. We will also describe the three templates of architecture in order to + be able to partition the application on the architecture. + \begin{livrable} + \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:7:0} + \setMacroInAuxFile{trtSpearde} + Adaptation of SPEAR-DE for COACH framework. + \end{livrable} +% + \subtask{\mds use case} + \mustbecompleted{\mds will use .................} + \begin{livrable} + \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0} + \setMacroInAuxFile{mdsAppSpecification} + \mustbecompleted{Adaptation of ...} + \end{livrable} + +\subtask{Evaluation report} + In this sub-task, \mds, \thales and \bull will evaluate the COACH platform. + The evaluation points are: + 1) the ability to generate a whole VHDL of an embedded system on FPGA for an application + mixing control and data flow aspects; + 2) the performance of the generated system in terms of GOPS; + 3) the design time from a high level description. + \begin{livrable} + \itemV{24}{30}{d+x}{\Smds}{\mds evaluation} + This deliverable is a document describing the result got for the application + (\mdsAppSpecification) using COACH milestone of T0+24. + \itemL{30}{36}{d+x}{\Smds}{\mds evaluation}{0:5:5} + This deliverable is a document that validates and evaluates COACH (final release) + for the \mds demonstrators (\mdsAppSpecification). +% + \itemV{24}{30}{d+x}{\Sbull}{\bull evaluation} + This deliverable is a document describing the result got for the application + (\bullAppSpecification) using COACH milestone of T0+24. + \itemL{30}{36}{d+x}{\Sbull}{\bull evaluation}{0:5:5} + This deliverable is a document that validates and evaluates COACH (final release) + for the \bull demonstrators (\bullAppSpecification). +% + \itemV{18}{24}{d+x}{\Sthales}{\thales evaluation} + This deliverable is a document describing the result got for the application + (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18. + The updated code of the application will be also provide. + \itemV{24}{30}{d+x}{\Sthales}{\thales evaluation} + This deliverable is a document describing the result got for the application + (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24. + The updated code of the application will be also provide. + \itemL{30}{36}{d+x}{\Sthales}{\thales evaluation}{0:5:5} + This deliverable is a document that validates and evaluates COACH (final release) + for the \thales demonstrators (\trtAppSpecification). + The updated code of the application will be also provide. + \end{livrable} + +\end{workpackage} Index: /anr/task-dissemination.tex =================================================================== --- /anr/task-dissemination.tex (revision 291) +++ /anr/task-dissemination.tex (revision 291) @@ -0,0 +1,76 @@ +\begin{taskinfo} +\let\MDS\leader +\let\ALL\enable +\end{taskinfo} +% +\begin{objectif} +This task relates to the diffusion of the project results. +The objective is to ensure the COACH dissemination by publishing on a public WEB site all +the information that a COACH user requires. +Those are: +\begin{itemize} + \item The packaging of COACH milestones and final release and their associated + installation manuals. + Two versions will be packaged (one open source, one commercial in the + Magillem environment). + \item A tutorial. + \item The user reference manuals. +\end{itemize} +\end{objectif} +% +\begin{workpackage} + \subtask{Packaging of COACH releases} + \begin{livrable} + \itemL{6}{36}{d+x}{\Supmc}{Open source release}{1:.5:.5} + \OtherPartner{12}{36}{\Stima}{0:2:1} + This deliverable deals with the packaging of the open sources milestones and + final releases with their installation manuals and to publish then into the WEB + site. This packaging will be done for standard Unix environment using + the usual open source installation configuration tools (automake, autoconf). + \itemL{6}{36}{d+x}{\Smds}{Commercial release}{1:.5:.5} + This deliverable deals with the elaboration of a release of COACH integrated + into the Magillem environment. + \end{livrable} +% + \subtask{Tutorial} + \label{subtask-tutorial} + The application of this tutorial will be a Motion JPEG application. + \begin{livrable} + \itemV{6}{12}{d+x}{\Supmc}{Tutorial} + It will illustrate the features the T0+12 milestone provides especially: + \begin{description} + \item[HPC] This tutorial section shows how an application can be split into + two communicating parts, the PC part and FPGA-SoC part, and how to + measure the quality of this partition. + \item[SoC] This tutorial section shows how FPGA-SoC part can be described as + communicating task graph. The tutorial also describes how a promising + task graph can be obtained. + \end{description} + \itemV{18}{24}{d}{\Supmc}{Tutorial} + \OtherPartner{12}{36}{\Smds}{0:2:2} + It will illustrate the HAS tools and architectural template available in + T0+24 milestone.\par + A section (written by \Supmc) will show how a task can be migrated to + coprocessor using HAS tools and how FPGA-SoC can be generated and run to + FPGA.\par + A section (written by \Smds) will be dedicated to the integration of + COACH generated IP into an IP-XACT based design flow (such as SOCKET). + \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1} + The final release of the tutorial. + \end{livrable} +% + \subtask{Reference user manuals} + \begin{livrable} + \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:1:0} + This user manual shows how to generate a complete HW/SW system by using CSG tool. + \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:1:0} + This user manual shows how to apply loop transformations to a task. + \itemL{18}{36}{d}{\Sirisa}{ASIP user manual}{0:1:1} + This user manual shows how to customize a processor to obtain an ASIP. + \itemL{18}{24}{d}{\Subs}{HLS user manual}{0:1:0} + This user manual shows how a task can be synthesized by using UGH and GAUT tools. + \OtherPartner{12}{36}{\Subs}{0:2:2} + \itemL{18}{36}{d}{\Smds}{Magillem framework user manual}{0:1:1} + This user manual describes how to use COACH within the IP-XACT based Magillem tool suite. + \end{livrable} +\end{workpackage} Index: /anr/task-frontend.tex =================================================================== --- /anr/task-frontend.tex (revision 291) +++ /anr/task-frontend.tex (revision 291) @@ -0,0 +1,83 @@ +\begin{taskinfo} +\let\LIP\leader +\let\IRISA\enable +\let\UBS\enable +\let\UPMC\enable +\let\TIMA\enable +\end{taskinfo} +% +\begin{objectif} +The objective of this task is to convert the input specification of +an hardware accelerator, which must be written in a familiar language +(C/C++) with as few constraints as possible, into a form suitable for +the HLS tools (i.e. HAS back-end tools of the COACH project). If the +target is an ASIP, the frontend has to extract +patterns from the source code and convert them into the definition +of an extensible processor. If the target is a process network, the +front end has to distribute the workload and the data sets as fairly +as possible, identify communication channels, and output an \xcoach +description. +\end{objectif} +% +\begin{workpackage} + \subtask{ASIP compiler} + This sub-task aims at providing compiler support for custom instructions + within the HAS front-end. It will take as input the COACH intermediate + representation, and will output an annotated COACH IR containing the custom + instructions definitions along with their occurrence in the application. + \begin{livrable} + \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow} + In this first version of the software, the computations patterns corresponding to + custom instructions are specified by the user, and then automatically extracted (when + beneficial) from the application intermediate representation. + \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0} + In this second version, the software will also be able to automatically identify + interesting pattern candidates in the application code, and use them as custom + instructions. + \end{livrable} + + \subtask{Micro-architectural template models for ASIP} + In this sub-task, we provide micro-architectural template models for the two target + processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. + For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) + of the architecture, along with its architectural extensions + \begin{livrable} + \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS } + { A SystemC simulation model for a simple extensible MIPS architectural template } + \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0} + {A SystemC simulation model for an extensible MIPS with a tight architectural integration of + its instruction set extensions} + \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS} + {A synthesizable VHDL model for a simple extensible MIPS architectural template} + \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0} + {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of + its instruction set extensions} + \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2} + {An evaluation report with quantitative analysis of the performance/area trade-off induced by + the different approaches} + \end{livrable} + + \subtask{Parallelism optimization} + Extraction of parallelism in polyhedral loops and conversion into a process network. + \begin{livrable} + \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition} + Description and specification of a process construction method for programs with + polyhedral loops. + \itemL{30}{36}{d}{\Slip}{Process generation method}{10:0:9} + Final assessment of the method and improved version of the specification. + \itemV{6}{12}{x}{\Slip}{Process construction} + Preliminary implementation in the Syntol framework. + At this step the software will just implement a single constructor. + \itemV{12}{18}{x}{\Slip} {Arrays and FIFO} + Implementation of the array contraction and FIFO construction algorithm. + Conversion of the input and output to the \xcoach format. + \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension} + Extension of automatic parallelization and array contraction + to non-polyhedral loops. Implementation in the Bee framework. + \itemL{30}{36}{x}{\Slip} {Process/FIFO construction}{10:20:12} + Final release taking into account the feedbacks from the + demonstrator \STs. + \end{livrable} + +\end{workpackage} + Index: /anr/task-hpc.tex =================================================================== --- /anr/task-hpc.tex (revision 291) +++ /anr/task-hpc.tex (revision 291) @@ -0,0 +1,96 @@ +% vim:set spell: +% vim:spell spelllang=en: + +\begin{taskinfo} +\let\BULL\leader +\let\UPMC\enable +\let\TIMA\enable +\let\THALES\enable +\let\XILINX\enable +\end{taskinfo} +% +\begin{objectif} +This task deals with the COACH HPC feature that consists in accelerating an existing +application running on a PC by migrating critical parts into a SoC implemented on an +FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}). +It consists in: +\begin{itemize} +\item Specifying and implementing the communication schemes between the software + part running on the PC and the FPGA-SoC. +\item Providing a performance analysis tool helping user in the HPC partitioning + (figure~\ref{archi-hpc}). +\item Providing support for configuration of the FPGA in order to set up the HPC environment. +\end{itemize} +The low level hardware transmission support will be the PCI/X bus which allows high bit-rate +transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for +their FPGA and that GPU HPC softwares use also it. +%This will allow us at least to be inspired by GPU communication schemes and may be to reuse +%parts of the GPU softwares. +\end{objectif} +% +\begin{workpackage} + \subtask{Implementation of API between PC and FPGA-SoC} + \begin{livrable} + \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} + \OtherPartner{0}{6}{\Supmc}{.5:0:0} + \OtherPartner{0}{6}{\Stima}{.5:0:0} + \setMacroInAuxFile{hpcCommApi} + Specification of the API. + \itemL{6}{12}{x}{\Supmc}{HPC partitioning helper}{1:0:0} + \setMacroInAuxFile{hpcCommHelper} + A library implementing the communication API defined in the {\hpcCommApi} deliverable. + This library is dedicated to help the end-user to partition an application for HPC. + \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0} + \setMacroInAuxFile{hpcCommLinux} + The PC part of the HPC communication API that communicates with the FPGA-SOC, a + library and a LINUX module. + \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} + \setMacroInAuxFile{hpcDnaDriver} + The FPGA-SoC part of the communication API (DNA driver). + \end{livrable} +% +\subtask{SystemC model of the PCI/X} + This \ST deals with the implementation of SystemC modules + required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. + \begin{livrable} + \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} + The SystemC description of a component that generates PCI/X traffic. It is + required to prototype FPGA-SoC dedicated to HPC. + \end{livrable} +% +\subtask{HPC environment set up} +% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. + \begin{livrable} + \itemL{18}{36}{x}{\Stima}{Support for HPC environment set up}{0:4:4} + Modification of the CSG software to set-up the HPC environment. + The objective is to run easily HPC application and the main features are: + automatic calibration of coprocessors (\freqCalibrationVhdl), automatic download of + SoC on FPGA (bitstream and application loader), starting the PC and FPGA + part of the HPC application. + \end{livrable} +% \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} +% This livrable is a CSG module allowing to partition the task graph along +% the dynamic partial reconfiguration regions. The resulting task-region assignement +% is directly used for generation of bitstreams. The module also produces reconfiguration +% management software to be run on the SoC-FPGA. +% \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3} +% \setMacroInAuxFile{hpcDynconfDriver} +% The drivers required by the DNA OS in order to manage dynamic partial +% reconfiguration inside the SoC-FPGA. +% \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for MUTEKH drivers}{0:0:1} +% Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. +% \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} +% Extension of the HPC partionning helper in order to integrate dynamic partial +% reconfiguration dedicated features (reconfiguration time of regions, variable +% number of coprocessors). +% \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2} +% \xilinx will work with \tima in order to better take into account during +% partitioning decisions specific constraints due to partial reconfiguration process. +% The deliverable is a document describing the \xilinx specific constraints. +% \end{livrable} +% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board +% % with its PCI/X IP. These boards are dedicated to the COACH HPC development. +% % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. +% % \begin{livrable} +% % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. +\end{workpackage} Index: /anr/task-management.tex =================================================================== --- /anr/task-management.tex (revision 291) +++ /anr/task-management.tex (revision 291) @@ -0,0 +1,54 @@ +\begin{taskinfo} +\let\MDS\leader +\let\ALL\enable +\end{taskinfo} +% +\begin{objectif} +This task relates to the monitoring of the COACH project. Its main objectives are: +\begin{itemize} +\item To ensure the appropriate progress of the project, +\item To coordinate the scientific and technical cooperation between the partners, +\item To manage and monitor the scientific and technical work and progress in the tasks, +\item To verify the conformance to agreed budget and time scales, +\item To prepare periodic progress reports in order to control the overall progress of the + project, +\item To organize the project meetings, +\item To set up a shared development infrastructure as a version control system and + development WEB site. +\end{itemize} +\end{objectif} +% +\begin{workpackage} + \subtask{Project management} + \begin{livrable} + \itemL{0}{6}{d}{\Smds}{Consortium agreement}{1:0:0} + A document describing the consortium agreement, signed by all the partners. + \itemL{0}{36}{d}{\Smds}{Global project management}{1:1:1} + Global management of the project at all the + levels: progress monitoring, record keeping, meeting organization, review + organization, the writing of the review reports. + \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5} + \OtherPartner{0}{36}{\Supmc}{.5:.5:.5} + \OtherPartner{0}{36}{\Subs} {.5:.5:.5} + \OtherPartner{0}{36}{\Stima}{.5:.5:.5} + \OtherPartner{0}{36}{\Slip} {.5:.5:.5} + \OtherPartner{0}{36}{\Sirisa} {.5:.5:.5} + \OtherPartner{0}{36}{\Sthales} {.5:.5:.5} + \OtherPartner{0}{36}{\Sbull} {.5:.5:.5} + Project management at the partner level. It includes mainly the progress + monitoring, the record keeping the participation to the project meetings + and the communication with the project leader and the other partners. + \end{livrable} + \subtask{Management of the development infrastructure} + \begin{livrable} + \itemV{0}{6}{x}{\Supmc}{Development \& dissemination infrastructure (setup)} + Setup of the development infrastructure. It consists mainly of + a version control system, a web site and a wiki. + \itemL{6}{36}{x}{\Supmc}{Development \& dissemination \ganttlf infrastructure}{1:.5:.5} + The management of the development infrastructure consists mainly of + adding \& suppressing account, retrieving forgotten passwords, adding + conference publications to web site, creation and closing development + branch, backup, restoration, .... + \end{livrable} +\end{workpackage} +%