Changeset 293 for anr


Ignore:
Timestamp:
Dec 12, 2010, 4:42:34 PM (14 years ago)
Author:
coach
Message:

Suppression de Xilinx qui trainait encore.

File:
1 edited

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  • anr/section-consortium-desc.tex

    r290 r293  
    167167
    168168%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    169 \subsubsection{\xilinx}
    170 
    171 \xilinx is the world leader in the domain of programmable logic circuits (FPGA).
    172 \xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex
    173 families) and on the other hand a software solution allowing exploiting the
    174 characteristics of these FPGA.
    175 \parlf
    176 The tools proposed allow the designer to describe his architecture from a modeling
    177 language (VHDL/Verilog) to an optimized architecture implemented to the selected
    178 technology.
    179 The team located at Grenoble is responsible of the logic synthesis tool development (XST)
    180 of the software solution, which aggregates all the steps allowing proceeding from a  HDL
    181 model to a technological netlist:
    182 \begin{itemize}
    183   \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
    184   \item RTL model optimizations.
    185   \item Inference and generation of optimized macro blocks (Finite states machine, counter).
    186   \item Boolean equations generation for random logic.
    187   \item Logical, mapping and timing optimizations.
    188 \end{itemize}
    189 \parlf
    190 The architectures developed by \xilinx offer a collection of technological primitives
    191 (variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
    192 and even configurable processor cores (Pico and MicroBlaze families).
    193 This kind of architecture allows, therefore, the designer to validate different
    194 hardware/software possibilities in a High Level Synthesis (HLS) framework.
    195 \parlf
    196 The classical optimization techniques focus, mainly, on the frequency aspects and on
    197 available resources use.
    198 The optimizations, taking into account the consumption criteria, become critical due to
    199 the fact of the increase of the architecture complexity and due to the use of FPGA
    200 component for low power applications.
    201 
    202 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    203169\subsubsection{\mdslong}
    204170
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