Changeset 293 for anr

Timestamp:

Dec 12, 2010, 4:42:34 PM (14 years ago)

Author:

coach

Message:

Suppression de Xilinx qui trainait encore.

File:

• anr/section-consortium-desc.tex (modified) (1 diff)

anr/section-consortium-desc.tex

@@ -167 +167 @@
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{\xilinx}
-
-\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
-\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex
-families) and on the other hand a software solution allowing exploiting the
-characteristics of these FPGA.
-\parlf
-The tools proposed allow the designer to describe his architecture from a modeling
-language (VHDL/Verilog) to an optimized architecture implemented to the selected
-technology.
-The team located at Grenoble is responsible of the logic synthesis tool development (XST)
-of the software solution, which aggregates all the steps allowing proceeding from a  HDL
-model to a technological netlist:
-\begin{itemize}
-  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
-  \item RTL model optimizations.
-  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
-  \item Boolean equations generation for random logic.
-  \item Logical, mapping and timing optimizations.
-\end{itemize}
-\parlf
-The architectures developed by \xilinx offer a collection of technological primitives
-(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
-and even configurable processor cores (Pico and MicroBlaze families).
-This kind of architecture allows, therefore, the designer to validate different
-hardware/software possibilities in a High Level Synthesis (HLS) framework.
-\parlf
-The classical optimization techniques focus, mainly, on the frequency aspects and on
-available resources use.
-The optimizations, taking into account the consumption criteria, become critical due to
-the fact of the increase of the architecture complexity and due to the use of FPGA
-component for low power applications.
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\mdslong}