Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 296) +++ /anr/anr.tex (revision 297) @@ -55,5 +55,5 @@ \definecolor{rouge}{rgb}{1.0,0.2,0.2} \def\mustbecompleted#1{} -\def\parlf{\noexpand\par\vspace*{1.0ex}} +\def\parlf{\mbox{}\vspace*{1.0ex}\\} \def\ADDED#1{\textcolor{blue}{#1}} \newenvironment{ADDEDENV}{\color{blue}}{} @@ -119,7 +119,7 @@ \begin{minipage}{\linewidth}Theme\\\end{minipage} & \setlength{\unitlength}{5.0mm}\begin{picture}(20,2) - \put( 0.5,1.1){\boitecochee} \put( 1.5,0.9){1} - \put( 3.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put( 4.5,0.9){2} - \put( 6.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put( 7.5,0.9){3} + \put( 0.5,0.9){\framebox(0.6,0.6){ }} \put( 1.5,0.9){1} + \put( 3.5,1.1){\boitecochee} \put( 4.5,0.9){2} + \put( 6.5,0.9){\framebox(0.6,0.6){}} \put( 7.5,0.9){3} \put( 9.5,0.9){\framebox(0.6,0.6){ }} \put(10.5,0.9){4} \put(12.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put(13.5,0.9){5} @@ -141,5 +141,5 @@ \vspace*{0.5ex}Total requested \\ funding \end{minipage} - & \makebox[3cm]{1195931 \euro} + & \makebox[3cm]{ \mustbecompleted{???} \euro} & \begin{minipage}{4.15cm}\center Project Duration \end{minipage} & \begin{minipage}{3cm}\center 36 months \end{minipage} \\\hline Index: /anr/section-1.tex =================================================================== --- /anr/section-1.tex (revision 296) +++ /anr/section-1.tex (revision 297) @@ -27,5 +27,4 @@ will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative devices and to enter new, low and medium volume markets. -\begin{ADDEDENV} Furthermore, today there is an increasing industrial interest to IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) @@ -34,17 +33,5 @@ general purpose CPU cores will contains a configurable area making explode the low and medium volume markets of digital systems. -\end{ADDEDENV} \parlf -\begin{SUPPRESSEDENV} -The objective of COACH is to provide an integrated design flow, based on the -SoCLib infrastructure~\cite{soclib}, and optimized for the design of -multi-processors digital systems targeting FPGA devices. -The digital systems are generally integrated into one or several chips, and there are two types of applications: -They can be embedded (autonomous) applications -such as personal digital assistants (PDA), ambient computing components, -or wireless sensor networks (WSN). -They can also be extension boards connected to a PC to accelerate a specific computation, -as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). -\end{SUPPRESSEDENV}\begin{ADDEDENV} The objective of COACH is to provide an integrated design flow for the design of multi-processors digital systems targeting FPGA devices. @@ -57,5 +44,4 @@ it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP); 3) sub-system application for generating an IP to a larger system. -\end{ADDEDENV} \parlf %verrous scientifiques et techniques @@ -70,8 +56,4 @@ For each point in the design space, metrics such as throughput, latency, power consumption, silicon area, memory allocation and data locality will be provided. - \begin{SUPPRESSEDENV} - These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure - and high-level estimation methodologies. - \end{SUPPRESSEDENV} \item[Hardware Accelerators Synthesis (HAS):] COACH will allow the automatic generation of hardware accelerators when required. @@ -106,6 +88,5 @@ communications between software tasks running on embedded processors and dedicated hardware coprocessors. -\begin{ADDEDENV} -\item[Interaction with the industrial world] +\item[Interaction with the industrial world:] COACH will not be a closed framework but it will be opened to the industrial world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the @@ -113,11 +94,5 @@ This should facilitate the enhancement of the architectural template with IP and the integration of the IP produced by COACH in larger design. -\end{ADDEDENV} \end{description} -\begin{SUPPRESSEDENV} -MOVED ABOVE -The COACH design flow will be dedicated to system designers, and will as -much as possible hide the hardware characteristics to the end-user. -\end{SUPPRESSEDENV} %From the end user point of view, the specification of the application will be %independant from both the architectural template and from the selected FPGA @@ -135,17 +110,9 @@ ASIP architectures (\irisa), High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip), -HPC (\bull, \thales), \mustbecompleted{XXX (\mds)}. +HPC (\bull, \thales), tools integration in IP-XACT flow (\mds). \\ The COACH project does not start from scratch. -\begin{SUPPRESSEDENV} -It strongly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, -(DSX, component library), operating systems (MUTEKH, DNA/OS). -It also leverages on several existing technologies: -on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, -on the ROMA~\cite{roma} project for ASIP, -on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations -and on the \xilinx and \altera IP core libraries. -\end{SUPPRESSEDENV}\begin{ADDEDENV} It relies +on the Magillem industrial platform for the integration into IP-XACT flows, on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS), on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, @@ -153,18 +120,7 @@ on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations, -on the \mustbecompleted{XXXX:magillem} for \mustbecompleted{XXXX:magillem}, and on the \xilinx and \altera IP core libraries. -\end{ADDEDENV} Finally it will use the \xilinx and \altera logic and physical synthesis tools to generate the FPGA configuration bitstreams. -\parlf -The COACH proposal has been prepared during one year by a technical working group -involving the 5 academic partners (one monthly meeting from january 2009 to february -2010). The objective was to analyse the issues of integrating -and enhancing the existing tools and technologies into a unique framework. -Most of the general software architecture of the proposed design flow (including the -exchange format specification) has been define by this working group. -\SUPPRESSED{Because the COACH project leanes on the ANR SoCLib platform, it may be -described as an extension of the SoCLib platform.} %The main development steps of the COACH project are: %\begin{enumerate} @@ -187,29 +143,19 @@ %\end{enumerate} \parlf -Two major FPGA companies are involved in the project: \xilinx will contribute -as a contractual partner providing documentation and manpower; \altera will contribute as -a supporter (see letter page \pageref{supp:1}) -providing documentation and development boards. These two companies are strongly motivated -to help the COACH project to generate efficient bitstreams for both FPGA families. The role of the industrial partners \bull, \thales and \mds is to provide real use cases to benchmark the COACH design environment and to analyze the designer productivity improvements. \parlf -\begin{SUPPRESSEDENV} -Following the general policy of the SoCLib platform, the COACH project will be an open -infrastructure, available in the framework of the SoCLib server. -The architectural templates, and the COACH software tools will be distributed under the -GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib -IP core library) will be freely available for non commercial use. -\end{SUPPRESSEDENV}\begin{ADDEDENV} -The COACH project will be an open infrastructure and freely distributed. -The architectural templates and the COACH software tools will be distributed under the -GPL license. The VHDL synthesizable models for the neutral architectural template +The COACH project will deliver an open and freely distributed infrastructure. +The architectural templates and most of the software tools will be distributed under the +GPL-like license. +The VHDL synthesizable models for the neutral architectural template will also be freely available for non commercial use. -\end{ADDEDENV} For industrial exploitation the technology providers are ready to propose commercial licenses, directly to the end user, or through a third party. \parlf \mustbecompleted{LIST NON A JOUR} +The major FPGA companies (\xilinx and \altera) have expressed their interest for +this project. Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the "letters of interest" (see Annex B), that have collected during the preparation of the project : Index: /anr/section-2.tex =================================================================== --- /anr/section-2.tex (revision 296) +++ /anr/section-2.tex (revision 297) @@ -8,7 +8,8 @@ software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling. Only very few SMEs have these multiple expertises and are present on the embedded system market. +Furthermore, even small design services in the big companies are facing the same issue. \begin{center}\begin{minipage}{.8\linewidth}\textit{ -The major objective of COACH is to provide to SMEs an open-source framework to design -embedded systems on FPGA devices by system designers. +The major objective of COACH is to provide to system designers, an affordable +open-source framework to design embedded systems on FPGA devices. }\end{minipage}\end{center} %Current design methodologies provide quite low-level abstraction capabilities, and @@ -19,6 +20,5 @@ %%% \parlf -The COACH project will leverage on the expertise gained in the field of virtual prototyping -with the SoCLib platform, to propose a new design flow based on a small number of architectural templates. +The COACH project will propose a new design flow based on a small number of architectural templates. An architectural template is a generic, parameterized architecture, relying on a predefined library of IP cores. @@ -42,6 +42,6 @@ When this interactive, system level, design space exploration is completed (converging to a specific mapping on a specific version of the selected architectural template), the rest of the flow -is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary -code for the software running on the embedded processors, and the bit-stream to program the the target FPGA +is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary +code for the software running on the embedded processors, and the bit-stream to program the target FPGA will be automatically generated by the COACH tools. % @@ -50,8 +50,9 @@ in a platform based design flow supporting virtual prototyping and design space exploration. Most building blocks already exist (resulting from previous projects): the GAUT -or UGH synthesis tools, the MUTEKH or DNA embedded operating systems, the ASIP technology, -the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool, -as well as the SoCLib library of systemC simulation models. They must now be enhanced and integrated in -a consistent design flow. +or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology, +the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool, +as well as the SoCLib library of SystemC simulation models. +They must now be enhanced and integrated in a consistent design flow: this will +be done in Magillem framework thanks to the IP-XACT standard. %The five academic laboratories worked very closely during more than one year (one monthly meeting %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating @@ -59,55 +60,12 @@ %%% \parlf -In HPC (High Performance Computing), the targeted application is an existing application +In HPC (High Performance Computing), the targeted application is an existing one running on a PC. The COACH framework helps designer to accelerate it by migrating critical parts into a SoC embedded into an FPGA device plugged to the PC PCI/X bus. \begin{center}\begin{minipage}{.8\linewidth}\textit{ -The second objective of COACH is to extend the framework to HPC. +The second objective of COACH is to extend the framework for HPC applications. }\end{minipage}\end{center} This will allow SMEs to enter HPC market for the applications that are unadapted to the current GPU based solutions. %%% -\parlf -In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks -have been previously developed by academic laboratories. - - -%Finally, the key points of the proposed design flow are : -%\begin{itemize} -%\item -%\textbf{System level exploration}: The application coarse grain parallelism -%is explicitely described as a Tasks and Communication Graph (TCG). -%A template architecture is selected, and the performances are evaluated -%on various variant of this architecture using the SoCLib virtual protyping -%environment. This result in a specific hardware/software partitioning. -%This system level exploration is fully controlled by the system designer, and is driven -%by cost, throughput, latency and power consumption criteria. -% -%\item -%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been -%identified as mandatory, they will be generated by the high level synthesis (HLS) tools. -%The COACH framework will integrate various HLS tools, supporting the micro-architectural space -%design exploration. Here again, the exploration criteria are cost, throughput, latency -%and power consumption. -%At this stage, preliminary source-level transformations and optimisations by front-end -%tools will be required to improve the efficiency of the back-end HLS tools. -% -%\item -%\textbf{Early performance evaluation}: For each point in the design space, -%figures of merit must be available such as throughput, latency, power -%consumption, area, memory allocation and data locality. They are evaluated -%by reliable estimators obtained by running the actual multi-task software -%application on the virtual prototype. -% -%\item -%\textbf{Independance from the Target FPGA}: The COACH description of the system -%(both hardware and software) should be independent of the FPGA family. -%Every point of the design space can be implemented on any FPGA component, -%as long as it contains the hardware ressources required by the selected architectural template. -%Basically, COACH will support both \altera and \xilinx FPGA families. -%\end{itemize} -% - - - Index: /anr/section-objectif.tex =================================================================== --- /anr/section-objectif.tex (revision 296) +++ /anr/section-objectif.tex (revision 297) @@ -11,7 +11,6 @@ % les objectifs scientifiques/techniques du projet. The design steps are presented figure~\ref{coach-flow}. -\ADDED{ The end-user input is -either a HPC application (an application running on a PC that must be accelarate), +either a HPC application (an application running on a PC that must be accelerate), or an embedded application (a standalone application), or a sub-system application of a larger design. @@ -19,5 +18,4 @@ except in the generation step and that the design flow of HPC application just adds a preliminary step. -} \begin{figure}[hbtp]\leavevmode\center \includegraphics[width=1.0\linewidth]{flow2} @@ -38,13 +36,4 @@ ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), and hardware (the process is implemented as a synthesized hardware coprocessor). -\begin{SUPPRESSEDENV} -\item[Application compilation:] -Once the SoC architecture is validated through performances analysis, -COACH will generate automatically an executable containing the host application and -the FPGA bitstream. This bitstream contains -both the hardware architecture and the SoC application software. -The user will be able to launch the application by -loading the bitstream on an FPGA and running the executable on PC. -\end{SUPPRESSEDENV}\begin{ADDEDENV} \item[Generation:] Once the SoC architecture is validated through performances analysis, @@ -55,5 +44,4 @@ also generated and the user will be able to launch the application by loading the bitstream on an FPGA and running the executable on PC. -\end{ADDEDENV} \end{description} Index: /anr/section-position.tex =================================================================== --- /anr/section-position.tex (revision 296) +++ /anr/section-position.tex (revision 297) @@ -37,4 +37,5 @@ \item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive environment, suitable for co-operative and distributed development. +\item \mustbecompleted{IP-XACT: .... MAGILLEM...} \end{itemize} COACH outcome will contribute to strengthen Europe's competitive position by developing @@ -53,17 +54,12 @@ \begin{description} \item[SOCLIB] - The SoCLib ANR platform (2007-2009) is an open infrastructure developped by - 10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 - industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). - It supports system level virtual prototyping of shared memory, multi-processors + The SoCLib ANR platform (2007-2009) is an open infrastructure + that supports system level virtual prototyping of shared memory, multi-processors architectures, and provides tools to map multi-tasks software application on these architectures, for reliable performance evaluation. The core of this platform is a library of SystemC simulation models for - general purpose IP cores such as processors, buses, networks, memories, IO controller. - The platform provides also embedded operating systems and software/hardware + general purpose IP cores. + It provides also embedded operating systems and software/hardware communication middleware. - The synthesisable VHDL models of IPs are not part of the SoCLib platform, and - COACH will enhance SoCLib by providing the synthesisable VHDL models required - for FPGA synthesis. \item[ROMA] The ROMA ANR project \cite{roma} involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D, @@ -92,15 +88,17 @@ CAIRN group in the context of the ANR BioWic project (2009-2011), so as to be able to validate the framework on real-life HPC applications. + \item[SoCket] \mustbecompleted{...... MAGILEM ......} + \item[HOSPI] \mustbecompleted{...... MAGILEM ......} + \item[SoftSoc] \mustbecompleted{...... MAGILEM ......} \end{description} %%% \parlf\noindent -The laboratories involved in the COACH project have a well estabished expertise -%in the following domains: -in the domains: +The partners involved in the COACH project have a well established expertise +in the following domains: \begin{itemize} \item In the field of High Level Synthesis (HLS), the project leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project - developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped + developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed by the \upmc and \tima laboratories. \item @@ -116,5 +114,5 @@ (Armor/Calife~\cite{CODES99} since 1996, and the Gecos compilers~\cite{ASAP05} since 2002). -\item + \item In the field of compilers, the \lip Compsys group was founded in 2002 by several senior researchers with experience in @@ -126,11 +124,12 @@ process construction \cite{Feau:96} and memory management \cite{bee} will be very useful as a front-end for HLS tools. + \item + Regarding \mustbecompleted{.... MAGILLEM ... IP-XACT} \end{itemize} %%% \parlf\noindent -The COACH project answers to several of the challenges found in different axis of the -call for proposals.%Keywords of the call are indicated below in italic writing. -\begin{description} -\item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\ +The COACH project totally fulfills the objectives of the axis 2 "METHODES, +OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES". +\mustbecompleted{BEGIN-FIXME} COACH will address new embedded systems architectures by allowing the design of Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design @@ -140,7 +139,5 @@ API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms. -\textbf{Thereby COACH well corresponds to axis 1}. -% -\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\ +\\ COACH will address High-Performance Computing (HPC) by helping designers to accelerate an application running on a PC. @@ -148,35 +145,8 @@ configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the PC bus (through a communication link like PCI/X). -Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance -as well as reducing the required area. -\textbf{Thereby COACH partially corresponds to axis 2}. -% -% IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et -% IA2PC: secondaire. -%VERS 3 -%\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\ -%Manufacturing technology employs more and more SoC. -%COACH will permit to design such complex digital systems. -%\textbf{Thereby COACH indirectly answers to axis 3 too}. - - -%\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\ -%VERS 1 -%Future control applications employ more and more SoC. -%Application domains for such systems are for example the automotive domain, as well as the -%aerospace and avionics domains. -%In all cases, high performance and real time requirements are combined with -%requirements to low power, low temperature, high dependability, and low cost.\\ -%Similary manufacturing, security and safety technologies require also more and more -%computation power. -%VERS 2 pour gagner de la place -%Manufacturing, controling, security and safety technologies employ more and more SoC. -%COACH will permit to design such complex digital systems. -%\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}. - -%\end{description} - -\item [Axis 3] \textit {Robotique et contr\^{o}le/commande}: - +\mustbecompleted{END-FIXME} +\parlf +The COACH project well fits also the axis 5 "USAGES". +\mustbecompleted{BEGIN-FIXME} COACH will address robotic and control applications by allowing to design complex systems based on MPSoC architecture. @@ -187,41 +157,11 @@ Manufacturing technology will also increasingly need high-end vision analysis and high-speed robot control. -\textbf{Thereby COACH indirectly answers to axis 3}. - -\item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}: - +% The results of the COACH project will help users to build cryptographic secure systems implemented in hardware or both in software/hardware in an effective way, substantially enhancing the process productivity of the cryptographic algorithms hardware synthesis, improving the quality and reducing the design time and the cost of synthesised cryptographic devices. -\textbf{Thereby COACH indirectly answers to axis 5}. - -\end{description} - -% IA2PC: 1) je ne vois pas trop ce que ca fait la. -% IA2PC: 2) c'est deja dans le 2.1 pour le small business. -% IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense -% IA2PC toujours que le large business est encore vise par COACH. -% IA2PC Alain a enleve toute reference sur ce large business. Sa raison est + -% IA2PC politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille -% IA2PC le message. Je partage assez son avis, la version actuelle est + claire que -% IA2PC celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses -% IA2PC boites. -% IA2PC -% IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large -% IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans -% IA2PC les sections precedentes. -% -% VERS 2 pour gagner de la place je l'enleve - -%PC2IA ok pas de probleme - -% COACH technologies can be used in both large and small business, as they will permit users to design -% embedded systems which meet a wide range of requirements: from low cost and low power consuming -% devices to very high speed devices, based on parallel computing. For enterprises that will use embedded -% systems designed via the approaches and tools targeted by COACH, there is the potential for greater -% efficiency, improved business processes and models. The net results: lower costs, faster response times, -% better service, and higher revenue. -%\parlf +\mustbecompleted{END-FIXME} +\parlf Finally, it is worth to note that this project covers priorities defined by the commission experts in the field of Information Technolgies Society (IST) for Embedded Index: /anr/section-project-description.tex =================================================================== --- /anr/section-project-description.tex (revision 296) +++ /anr/section-project-description.tex (revision 297) @@ -40,6 +40,6 @@ controls the HAS tools described below. From these inputs \verb!CSG! can generate the entire system (both software and -hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger -design or} +hardware) either as an IP under IP-XACT to integrate the SoC in larger +design or as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and @@ -47,10 +47,8 @@ FPGA device\footnote{Additional partial bitstreams are generated in case of dynamic partial reconfiguration}. - \begin{ADDEDENV} \\ Furthermore the architecture template and hardware component libraries will be described - under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other + under the IP-XACT specification to facilitate the configuration of \verb+CSG+ to other architecture or the enhancement of existing template with IP. - \end{ADDEDENV}% \parlf The software architecture for HAS is presented in figure~\ref{archi-hls}.