Index: /anr/annexe-autre-participation.tex =================================================================== --- /anr/annexe-autre-participation.tex (revision 303) +++ /anr/annexe-autre-participation.tex (revision 304) @@ -21,8 +21,8 @@ \autreprojettabularentry {5}{Greiner}{13} - {\mustbecompleted{FIXME-exemple}Tsar, UE, 200 k\euro} - {\mustbecompleted{Term Smart Argh Real}} - {Dupont} - {01/01/2008 12/31/2010} + {Tsar, CATRENE, 500 k\euro} + {Tera Scale ARchitecture} + {Nam Nguyen (Bull)} + {01/01/2008 05/31/2011} \end{autreprojettabular} Index: /anr/annexe-cv.tex =================================================================== --- /anr/annexe-cv.tex (revision 303) +++ /anr/annexe-cv.tex (revision 304) @@ -19,4 +19,18 @@ \begin{cvenv} + {{Greiner}{Alain}{58}} + {Professeur UMPC} + {HDR Thesis (1982)} + {{100}{\cite{ag-1} \cite{ag-2} \cite{ag-3} \cite{ag-4}}} + + \item[Projects]\mbox{} + \begin{itemize} + \item Work on TSAR CATRENE project \cite{disydent05}. + \item Worked on SoCLib ANR project\cite{disydent05}. + \item Worked on COSY european project \cite{cosy}. + \end{itemize} +\end{cvenv} +% +\begin{cvenv} {{Aug\'e}{Ivan}{50}} {Ma\^itre de conf\'erences at ENSIIE (Evry Essonne)} Index: /anr/anr.bib =================================================================== --- /anr/anr.bib (revision 303) +++ /anr/anr.bib (revision 304) @@ -761,2 +761,68 @@ } +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% AG + +@article{ag-1, + author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi}, + title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components}, + journal ={On-Line Testing Symposium, IEEE International}, + volume = {0}, + isbn = {978-1-4244-7724-1}, + year = {2010}, + pages = {194-196}, + doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209}, + publisher = {IEEE Computer Society}, + address = {Los Alamitos, CA, USA}, +} + +@inproceedings{ag-2, + author = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela}, + title = {A Generic Hardware/Software Communication Middleware for + Streaming Applications on Shared Memory Multi Processor Systems-on-Chip}, + booktitle = {Forum on Specification \& Design Languages (FDL 2009)}, + isbn = { 978-2-9530504-1-7}, + month = {September}, + year = {2009}, + address = {Nice, France}, +} + +@inproceedings{ag-3, + author = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain}, + title = {Multi-compartment: A new architecture for secure + co-hosting on SoC }, + booktitle = {Proceedings of the 11th international conference on System-on-chip}, + series = {SOC'09}, + month = {October}, + year = {2009}, + isbn = {978-1-4244-4466-3}, + location = {Tampere, Finland}, + pages = {124-127}, + numpages = {4}, + url = {http://portal.acm.org/citation.cfm?id=1736530.1736555}, + publisher = {IEEE Press}, + address = {Piscataway, NJ, USA}, +} + +@inproceedings{ag-4, + author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain}, + title = {Physical Implementation of the DSPIN Network-on-Chip in the + FAUST Architecture}, + booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip}, + series = {NOCS'08}, + year = {2008}, + month = {April}, + isbn = {978-0-7695-3098-7}, + location = {Newcastle, UK}, + pages = {139-148}, + numpages = {10}, + url = {http://portal.acm.org/citation.cfm?id=1397757.1397994}, + publisher = {IEEE Computer Society}, + address = {Washington, DC, USA}, +} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% XXXX + Index: /anr/anr.sty =================================================================== --- /anr/anr.sty (revision 303) +++ /anr/anr.sty (revision 304) @@ -1,6 +1,2 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\catcode`\@=11 -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% - %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newlength{\desclen} @@ -8,30 +4,29 @@ \newlength{\mmlen} -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%{\catcode`\<=1\catcode`\>=2 -% <\catcode`\{=12\gdef\OBraceTw<{>> -% <\catcode`\}=12\gdef\CBraceTw<}>> -%> -%\@ifundefined{specHasManual}{\let\specHasManual\relax}{} +\newbox\livrable@box +\newbox\tmp@box + \let\specHasManual\relax \let\specCsgManual\relax -\let\specXilinxOptimization\relax - + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \def\eoa{end-of-args} \def\@@novers#1-#2\eoa{#1} \def\@novers#1{\ifx\relax#1\def\next{{\color{red}FIXME}}\else\def\next{\expandafter\@@novers#1\eoa}\fi\next} -\def\setMacroInAuxFile#1{% - \hypertarget{#1}{}\vspace{-1.5ex}% - \let\@novers\relax% - \global\expandafter\edef\csname NOLNK#1\endcsname{\name}% - \global\expandafter\edef\csname #1\endcsname{\noexpand\hyperlink{#1}{\name}}% - \global\expandafter\edef\csname NOVERS#1\endcsname{\noexpand\hyperlink{#1}{\@novers{\name}}}% - \global\expandafter\edef\csname NOVL#1\endcsname{\@novers{\name}}% - \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOLNK#1\endcsname{\name}}% - \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname #1\endcsname{\string\hyperlink{#1}{\name}}}% - \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVERS#1\endcsname{\string\hyperlink{#1}{\@novers{\name}}}}% - \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVL#1\endcsname{\@novers{\name}}}% -} +\def\@hypertarget@cor{0pt} +\def\setMacroInAuxFile#1#2{% +%\mbox{}{\hypertarget{#1}{}\vspace{-1.0ex}}% +\hypertarget{#1}{}\gdef\@hypertarget@cor{1.5ex}% +\let\@novers\relax% +\global\expandafter\edef\csname NOLNK#1\endcsname{\name}% +\global\expandafter\edef\csname #1\endcsname{\noexpand\hyperlink{#1}{\name}}% +\global\expandafter\edef\csname NOVERS#1\endcsname{\noexpand\hyperlink{#1}{\@novers{\name}}}% +\global\expandafter\edef\csname NOVL#1\endcsname{\@novers{\name}}% +\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOLNK#1\endcsname{\name}}% +\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname #1\endcsname{\string\hyperlink{#1}{\name}}}% +\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVERS#1\endcsname{\string\hyperlink{#1}{\@novers{\name}}}}% +\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVL#1\endcsname{\@novers{\name}}}% +#2} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -82,4 +77,19 @@ \newwrite\ganttdata \immediate\openout\ganttdata=anr.gantt +\def\write@ganttdata#1{{ + \let\xcoach\relax% + \let\xcoachplus\relax% + \let\irisa\relax \let\Sirisa\relax% + \let\lip\relax \let\Slip\relax% + \let\tima\relax \let\Stima\relax% + \let\ubs\relax \let\Subs\relax% + \let\upmc\relax \let\Supmc\relax% + \let\altera\relax \let\Saltera\relax% + \let\bull\relax \let\Sbull\relax% + \let\thales\relax \let\Sthales\relax% + \let\mds\relax \let\Smds\relax% + \let\xilinx\relax% + \immediate\write\ganttdata{#1} +}} \def\enable{enable} @@ -133,157 +143,169 @@ \newcount\subtaskcnt \newcount\livrablecnt -\newenvironment{workpackage}% -{\global\advance\taskcnt1 - \global\subtaskcnt0 - \def\taskname{T\the\taskcnt}% - \begin{description}% - %\let\itemsave\item% - \def\subtask##1{% + + \def\@subtask#1{% \global\advance\subtaskcnt1 \def\subtaskname{S\taskname-\the\subtaskcnt}% - \item[\subtaskname: ##1]% + \write@ganttdata{STN=\the\taskcnt\space\the\subtaskcnt\space#1}% + \item[\subtaskname: #1]% \IfFileExists{tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex}% {(\input{tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex})}% {\message{SKIPPING tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex files}}% - \mbox{}\\% - {% - \let\xcoach\relax% - \let\xcoachplus\relax% - \let\irisa\relax \let\Sirisa\relax% - \let\lip\relax \let\Slip\relax% - \let\tima\relax \let\Stima\relax% - \let\ubs\relax \let\Subs\relax% - \let\upmc\relax \let\Supmc\relax% - \let\altera\relax \let\Saltera\relax% - \let\bull\relax \let\Sbull\relax% - \let\thales\relax \let\Sthales\relax% - \let\mds\relax \let\Smds\relax% - \let\xilinx\relax% - \immediate\write\ganttdata{% - STN=\the\taskcnt\space\the\subtaskcnt\space##1 - }% - }}% -}{% - \end{description}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\writeganttinfo#1#2#3#4#5#6{{% - \let\xcoach\relax - \let\xcoachplus\relax - \let\irisa\relax \let\Sirisa\relax - \let\lip\relax \let\Slip\relax - \let\tima\relax \let\Stima\relax - \let\ubs\relax \let\Subs\relax - \let\upmc\relax \let\Supmc\relax - \let\altera\relax \let\Saltera\relax - \let\bull\relax \let\Sbull\relax - \let\thales\relax \let\Sthales\relax - \let\mds\relax \let\Smds\relax - \let\xilinx\relax - \immediate\write\ganttdata{% + \mbox{}\\% +} + +\newenvironment{workpackage}{% + \global\advance\taskcnt1% + \global\subtaskcnt0% + \def\taskname{T\the\taskcnt}% + \begin{description}% + \let\subtask\@subtask% +}{ \end{description}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\def\writeganttinfo#1#2#3#4#5#6{% + \write@ganttdata{% L=1 T=\the\taskcnt\space S=\the\subtaskcnt\space% D=\the\livrablecnt\space V=\vers\space% BM=#1 EM=#2 R=#3 PART={#4} KIND={#5} TITLE=#6% - } -}} -\newenvironment{livrable}% -{% - \newcount\verscnt\verscnt=-1 - \newif\ifIsLivrableStarted\IsLivrableStartedfalse - \newif\ifLivrableTopLine\LivrableTopLinetrue - \def\livrableTableDef{\begin{tabular}{|c|c|c|c|p{.625\linewidth}|}\hline} - \def\livrableTableLine##1##2##3##4{% - \makebox[3.5em]{\begin{small}##1\end{small}} & - \makebox[2.2em]{\begin{small}##2\end{small}} & - \makebox[1.5em]{\begin{small}##3\end{small}} & - \makebox[2.2em]{\begin{small}##4\end{small}} & - } - \def\livrableTableTopLine{% - \livrableTableLine{number}{date}{type}{resp.} description - } - \livrablecnt-1 + }% +} + +\def\livrable@description@width{13.5cm} +\def\livrable@description@width{10.4cm} +\newif\if@livrable@firsttable@ +\newif\if@livrable@table@MustBeOpened@ +\newif\if@livrable@table@MustBeClosed@ +\newif\if@livrable@table@MustBeClosed@after@ +\let\librable@table@print@addon\relax +\def\livrable@table@begin{\begin{tabular}{|p{3.5em}|c|c|c|l|}\hline} +\def\livrable@table@line#1#2#3#4#5#6{ + \makebox[3.5em][c]{\begin{small}#1\end{small}} & + \makebox[2.2em]{\begin{small}#2\end{small}} & + \makebox[1.5em]{\begin{small}#3\end{small}} & + \makebox[2.2em]{\begin{small}#4\end{small}} & + #5\\#6} +\def\livrable@table@end{\end{tabular}\\} +\def\livrable@print@table{% + \if@livrable@table@MustBeOpened@% + \livrable@table@begin% + \global\@livrable@table@MustBeOpened@false% + \fi% + \if@livrable@firsttable@% + \livrable@table@line{number}{date}{type}{resp.}{description}{\hline\hline}% + \fi% + \global\@livrable@firsttable@false% + \livrable@table@line% + {\textsc{\name}}% + {\textsc{T0+\livrableEndDate}}% + {\textsc{\livrableType}}% + {\textsc{\livrableLeader}}% + %{\mbox{\copy\livrable@box}}{\hline}% + %{\raisebox{\@hypertarget@cor}[\ht\livrable@box][\ht\livrable@box]{\copy\livrable@box}\librable@table@print@addon\vspace*{1pt}}{\hline}% + {\raisebox{\@hypertarget@cor}{\copy\livrable@box}\librable@table@print@addon\vspace*{1pt}}{\hline}% +% {}{\cline{2-5}}% +% %& \multicolumn{4}{l|}{\raisebox{\@hypertarget@cor}{\copy\livrable@box}}\\\hline% +% & \multicolumn{4}{l|}{{\copy\livrable@box}}\\\hline% + \if@livrable@table@MustBeClosed@% + \livrable@table@end% + \global\@livrable@table@MustBeOpened@true% + \global\@livrable@table@MustBeClosed@false% + \fi% + \if@livrable@table@MustBeClosed@after@% + \global\@livrable@table@MustBeClosed@true% + \global\@livrable@table@MustBeClosed@after@false% + \fi% + \global\def\@hypertarget@cor{0pt}% + \global\let\librable@table@print@addon\relax% +} + +\def\@livrable@desc@box@start{% + \begin{lrbox}{\livrable@box}\begin{minipage}[t]{\livrable@description@width}% + \fontsize{11.0pt}{10pt}\selectfont% + \let\ia@description\description% + \def\description{\vspace*{-1.5ex}\ia@description\itemsep=1pt\topsep2pt\parskip0pt}% + %\let\ia@enddescription\enddescription% + %\newenvironment{description}{% + %}{\ia@enddescription}% +} + +\def\@livrable@desc@box@start@eatCR#1{\@livrable@desc@box@start#1} +%\def\tmp{ +%} +%\def\eat{\message{AAAAAAAAAAAAA:EAT}\@livrable@desc@box@start} +%\if\noexpand\nexttok\tmp +% \message{AAAAAAAAAAAAAAAAAAAAA:OUI}% +% \def\cont{\eat}% +%\else% +% \message{AAAAAAAAAAAAAAAAAAAAA:NON}% +% \def\cont{\@livrable@desc@box@start}% +%\fi% +%\cont} + + +\def\@itemV@next#1#2#3#4#5{\livrable@print@table\@itemV@first{#1}{#2}{#3}{#4}{#5}} +\def\@itemV@first#1#2#3#4#5{% + \def\vers{V\the\verscnt}% + \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% + \global\def\librable@table@print@addon{\hypertarget{\name}{}}% + \gdef\livrableEndDate{#2}% + \gdef\livrableType{#3}% + \gdef\livrableLeader{#4}% + \def\itemV{\end{minipage}\end{lrbox}\global\advance\verscnt1\global\setbox\livrable@box=\copy\livrable@box\@itemV@next}% + \def\itemL{\end{minipage}\end{lrbox}\global\advance\verscnt1\global\setbox\livrable@box=\copy\livrable@box\@itemL@next}% + \writeganttinfo{#1}{#2}{none}{#4}{#3}{#5}% + \futurelet\nexttok\@livrable@desc@box@start@eatCR% +} +% \parskip0pt \topsep0pt \parsep0pt \itemsep0pt \partopsep0pt + +\def\@itemL@next#1#2#3#4#5#6{\global\@livrable@table@MustBeClosed@after@true\livrable@print@table\@itemL@first{#1}{#2}{#3}{#4}{#5}{#6}} +\def\@itemL@first#1#2#3#4#5#6{% + \def\vers{VF}% + \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% + \global\def\librable@table@print@addon{\hypertarget{\name}{}\hypertarget{\expandafter\@@novers\name\eoa}{}}% + \gdef\livrableEndDate{#2}% + \gdef\livrableType{#3}% + \gdef\livrableLeader{#4}% + \def\itemV{\end{minipage}\end{lrbox}\global\advance\livrablecnt1\global\verscnt1\global\setbox\livrable@box\copy\livrable@box\@itemV@next}% + \def\itemL{\end{minipage}\end{lrbox}\global\advance\livrablecnt1\global\verscnt1\global\setbox\livrable@box\copy\livrable@box\@itemL@next}% + \writeganttinfo{#1}{#2}{#6}{#4}{#3}{#5}% + %\gdef\baselinestretch{2.50}XXX\\% + \global\@livrable@table@MustBeClosed@true + \futurelet\nexttok\@livrable@desc@box@start@eatCR% +} + +\newenvironment{livrable}{% + \newcount\verscnt\verscnt=1 + \livrablecnt0 + \def\livrableTableDef{\begin{tabular}{|p{3.5em}|c|c|c|p{.625\linewidth}|}\hline} \ifvmode \else\par\fi - - \def\itemV##1##2##3##4##5{% - \ifIsLivrableStarted - \global\advance\verscnt1 - \else - \global\advance\livrablecnt1 - \global\verscnt1 - \fi - \def\vers{V\the\verscnt} - \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% - \hypertarget{\name}{}% - \writeganttinfo{##1}{##2}{none}{##4}{##3}{##5} - \\\hline - \ifLivrableTopLine - \ifIsLivrableStarted\else\hline\hline\fi - \else - \ifIsLivrableStarted\else\end{tabular}\\\livrableTableDef\fi - \fi - \global\LivrableTopLinefalse - \global\IsLivrableStartedtrue - %\global\LivrableStartfalse - \livrableTableLine% - {\textsc{\name}}% - {\textsc{T0+##2}}% - {\textsc{##3}}% - {\textsc{##4}}% - } - \def\itemL##1##2##3##4##5##6{% - \ifIsLivrableStarted - %\global\advance\verscnt1 - \else - \global\advance\livrablecnt1 - %\global\verscnt1 - \fi - \def\vers{VF} - \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% - \hypertarget{\name}{}% - \hypertarget{\expandafter\@@novers\name\eoa}{}% - \writeganttinfo{##1}{##2}{##6}{##4}{##3}{##5} - \\\hline - \ifLivrableTopLine - \ifIsLivrableStarted\else\hline\hline\fi - \else - \ifIsLivrableStarted\else\end{tabular}\\\livrableTableDef\fi - \fi - \global\LivrableTopLinefalse - \global\IsLivrableStartedfalse - %\global\LivrableStartfalse - \livrableTableLine% - {\textsc{\name}}% - {\textsc{T0+##2}}% - {\textsc{##3}}% - {\textsc{##4}}% - } - \def\OtherPartner##1##2##3##4{{% - \let\xcoach\relax - \let\xcoachplus\relax - \let\irisa\relax \let\Sirisa\relax - \let\lip\relax \let\Slip\relax - \let\tima\relax \let\Stima\relax - \let\ubs\relax \let\Subs\relax - \let\upmc\relax \let\Supmc\relax - \let\altera\relax \let\Saltera\relax - \let\bull\relax \let\Sbull\relax - \let\thales\relax \let\Sthales\relax - \let\mds\relax \let\Smds\relax - \immediate\write\ganttdata{% - L=0 T=\the\taskcnt\space S=\the\subtaskcnt\space% - D=\the\livrablecnt\space BM=##1 EM=##2 R=##4 PART={##3} TITLE=% - } - }} -% \begin{small} - \livrableTableDef - \livrableTableTopLine - %\begin{tabular}{|c|c|c|c|p{.55\linewidth}|}\hline% - %\makebox[3.5em]{number} & \makebox[1.5em]{date} & type & resp. & description -} -{\\\hline\end{tabular}\\% -%\end{small}\\% -} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\catcode`\@=12 -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\def\OtherPartner##1##2##3##4##5{{% +\let\xcoach\relax% +\let\xcoachplus\relax% +\let\irisa\relax\let\Sirisa\relax% +\let\lip\relax\let\Slip\relax% +\let\tima\relax\let\Stima\relax% +\let\ubs\relax\let\Subs\relax% +\let\upmc\relax\let\Supmc\relax% +\let\altera\relax\let\Saltera\relax% +\let\bull\relax\let\Sbull\relax% +\let\thales\relax\let\Sthales\relax% +\let\mds\relax\let\Smds\relax% +\immediate\write\ganttdata{% + L=0 T=\the\taskcnt\space S=\the\subtaskcnt\space% + D=\the\livrablecnt\space BM=##1 EM=##2 R=##4 PART={##3} TITLE=% +}% +}##5} + \let\itemV\@itemV@first + \let\itemL\@itemL@first + \@livrable@firsttable@true + \@livrable@table@MustBeOpened@true + \@livrable@table@MustBeClosed@false + \@livrable@table@MustBeClosed@after@false + \def\@hypertarget@cor{0pt} +}{% + \end{minipage}\end{lrbox}\global\setbox\livrable@box=\copy\livrable@box% + \@livrable@table@MustBeClosed@true\livrable@print@table% +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Index: /anr/section-consortium-people.tex =================================================================== --- /anr/section-consortium-people.tex (revision 303) +++ /anr/section-consortium-people.tex (revision 304) @@ -54,7 +54,7 @@ \peopletabularentry{\upmc} -responsible & Greiner & Alain & professor & SOC ... & 13 & Expertise in MPSoC design, virtual prototyping, micro-architecture. +responsible & Greiner & Alain & professor & SOC & 12 & Expertise in MPSoC design, virtual prototyping, micro-architecture. Responsible of Task-2. Participation to Task-3/6. \\\hline -member & Aug\'{e} & Ivan & assistant professor & HLS SOC HPC & 13 & Expertise in HLS, software development, kernel, SoC design, micro-architecture. +member & Aug\'{e} & Ivan & assistant professor & HLS SOC HPC & 16 & Expertise in HLS, software development, kernel, SoC design, micro-architecture. Responsible of Task-3. Participation to Task-2/5/6/8. \\\hline Index: /anr/section-project-task-schedule.tex =================================================================== --- /anr/section-project-task-schedule.tex (revision 303) +++ /anr/section-project-task-schedule.tex (revision 304) @@ -14,5 +14,5 @@ \definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7} \definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4} -\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24} +\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=27} %\def\ganttlabelstyle#1{\begin{small}#1\end{small}} \def\ganttlabelstyle#1{\begin{small}\hyperlink{#1}{#1}\end{small}} @@ -49,11 +49,14 @@ %The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project. Before the final release (T0+36), there are 4 milestones (red lines on the figures) at -$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent +$T0+6$, $T0+12$, $T0+18$ and $T0+27$ that are rendez-vous points of the precedent deliverables. \begin{description} -\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of + \item[Milestone 1 ($T0+6$)] + Specification of COACH inputs, of the \xcoach format and of the demonstatrors as a reference software. -\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are - written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC. + \item[Milestone 2 ($T0+12$)] + The first COACH release. At this step the demonstrators are + written in the COACH input format. This COACH release allows to prototype + and to generate the FPGA-SoC. The main restrictions are: 1) Only the neutral architectural template is supported, @@ -61,31 +64,35 @@ 3) Enhanced communication schemes are not available. 4) ASIP compilation flow is not available. -\item[Milestone 3 ($T0+18$)] The second COACH release. At this step most of the COACH - features are availables. A preliminary version of the ASIP synthesis flow is supported, for a - simple extensible MIPS model. The main restriction is that COACH can not yet - generate FPGA-SoC for \altera and \xilinx architectural templates. + \item[Milestone 3 ($T0+18$)] + The second COACH release. At this step most of the COACH features are available. + A preliminary version of the ASIP synthesis flow is supported, for a + simple extensible MIPS model. The main restriction is that COACH can not yet + generate FPGA-SoC for \altera and \xilinx architectural templates. The others restriction is that the HAS tools are not yet fully operational. -\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is - supported. - The main restriction are: - 1) The backend HAS tools have not been yet enhanced, - 2) Dynamic partial reconfiguration is not supported, - 3) NIOS processor instruction set extension is supported, but only for user specified patterns. +\item[Milestone 4 ($T0+27$)] + The pre-release of the COACH project. The full design flow is supported. + The main restrictions are: + 1) Automatic frequency calibration of coprocessor is not available. + 2) Automatic HPC set up is not yet available. + 3) NIOS processor instruction set extension is supported, but only for user + specified patterns. + 4) GAUT enhencements are not available. \item[Final Release ($T0+36$)] - + \end{description} -This organisation allows the project to globally progress step by step mixing development -and demonstrator deliverables. -Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility -at the integration phase is significantly reduced. +This organisation allows the project to globally progress step by step mixing +development and demonstrator deliverables. +Hence, demonstrator feed-back will arrive early and so the risk to point out +incompatibility at the integration phase is significantly reduced. \par The risks that have been identified at the beginning of the project are the following: \begin{description} -\item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})] - Partners have to agree on a convenient exchange format for all tools involved. - Because all the HAS tools rely on it, the \xcoach format specification is a - crucial step. There are no work-around but as mentionned in - section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it - for a full year and a preliminary document already exists. + \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})] + Partners have to agree on a convenient exchange format for all tools involved. + Because all the HAS tools rely on it, the \xcoach format specification is a + crucial step. + There are no work-around but as mentionned in section~\ref{xcoach-problem} + (page~\pageref{xcoach-problem}) the five academic partners have worked on it + for a full year and a preliminary document already exists. %\item[\xcoachplus format (\novers{\specXcoachDoc}, % \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] @@ -93,20 +100,37 @@ % By centralizing the coprocessor generation, it guarantees their functioning % independently of the used HAS tools. -% Our experience with UGH and GAUT give us confidence in the succes of this -% task. -\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\NOVERScsgImplementation})] - The SoCLib component library contains several SystemC models used for the virtual - prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores). - Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped. - If the workload of this simulation model development is too important, virtual prototyping - of those architectural templates will not be directly supported. - The three architectural templates being quite similar, the virtual - prototyping will use the neutral architectural template. -\item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})] - If one of these tasks is impossible or too important or leads to inefficiency, - it will be abandoned. - In this case, the neutral architectural template will not be available for HPC and - a SystemC VCI model corresponding to the PCI/X IP will be developped to allow - virtual prototyping. +% Our experience with UGH and GAUT give us confidence in the succes of this +% task. + \item[Virtual prototyping ({\NOVERScsgImplementation})] + In this project, only the virtual prototyping of the neutral architectural + template is supported. + We think that this restriction is not a serious problem. + Indeed the \altera \& \xilinx architectural templates being architecturally close of + the neutral architectural template, an efficient software/hardware partition + on the neutral architectural template is also an efficient on the other + architectural templates. + The project will allow to verify experimentally this assumption. +% \item[Virtual prototyping of \altera \& \xilinx architectural templates +% ({\NOVERScsgImplementation})] +% The SoCLib component library contains several SystemC models used for the +% virtual prototyping of the \altera and \xilinx architectural templates +% (NIOS and Microblaze processor cores). +% Nevertheless, at this time we do not know how many IP cores SystemC +% simulation models have to be developped. +% If the workload of this simulation model development is too important, +% virtual prototyping of those architectural templates will not be directly +% supported. +% The three architectural templates being quite similar, the virtual +% prototyping will use the neutral architectural template. + \item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})] + These bridges may decrease the efficiency of the \altera \& \xilinx + architectural templates. + Developing the communication components (MWMR) for the AVALON and PLB buses + will correct this problem. +% If one of these tasks is impossible or too important or leads to inefficiency, +% it will be abandoned. +% In this case, the neutral architectural template will not be available for HPC and +% a SystemC VCI model corresponding to the PCI/X IP will be developped to allow +% virtual prototyping. \end{description} \parlf Index: /anr/section-ressources.tex =================================================================== --- /anr/section-ressources.tex (revision 303) +++ /anr/section-ressources.tex (revision 304) @@ -187,5 +187,5 @@ non-permanent personnels. The detail by deliverables is given in figure~\ref{table-livrables-2}. - The non-permanent personnels costs represent 50\% of the personnal costs. + The non-permanent personnels costs (24 \hommemois) represent 46\% of the personnal costs. The requested funding for non permanent personnels is 79\% of the total ANR requested funding. Index: /anr/task-backbone.tex =================================================================== --- /anr/task-backbone.tex (revision 303) +++ /anr/task-backbone.tex (revision 304) @@ -80,6 +80,6 @@ developers of HAS tools suggested. \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{7:3:0} - \OtherPartner{0}{18}{\Supmc} {.5:0:0} - \OtherPartner{0}{18}{\Stima} {.5:0:0} + \OtherPartner{0}{18}{\Supmc} {.5:.5:0} + \OtherPartner{0}{18}{\Stima} {.5:.5:0} \setMacroInAuxFile{specXcoachDoc} Last release of XML specification of the \xcoach format enhanced with @@ -101,5 +101,5 @@ The first release of the software tool X2SC that translates \xcoachplus description to CABA and TLM-DT SystemC module. - \itemL{18}{24}{x}{\Supmc}{X2SC tool}{0:1.5:0} + \itemL{18}{27}{x}{\Supmc}{X2SC tool}{0:1:.5} \setMacroInAuxFile{specXcoachToSystemC} Final release of the former software (\specXcoachToSystemCI). @@ -108,5 +108,5 @@ The first release of the software tool X2VHDL that translates \xcoachplus description to synthesizable VHDL description. - \itemL{18}{24}{x}{\Subs}{X2VHDL tool}{0:3:0} + \itemL{18}{27}{x}{\Subs}{X2VHDL tool}{0:2:1} \setMacroInAuxFile{specXcoachToVhdl} Final release of the former software (\specXcoachToVhdlI). Index: /anr/task-backend.tex =================================================================== --- /anr/task-backend.tex (revision 303) +++ /anr/task-backend.tex (revision 304) @@ -39,8 +39,8 @@ \itemV{12}{18}{x}{\Stima}{UGH integration} UGH release that interprets the task communication API. - \itemV{18}{24}{x}{\Supmc}{UGH integration} + \itemV{18}{27}{x}{\Supmc}{UGH integration} UGH release that writes \xcoachplus format. - \itemL{24}{36}{x}{\Stima}{UGH integration}{3:3:1} - \OtherPartner{0}{12}{\Supmc}{1:3:1} + \itemL{27}{36}{x}{\Stima}{UGH integration}{3:3:1} + \OtherPartner{0}{12}{\Supmc}{1:2.5:1} UGH release taking into account demonstrator's feedback. % @@ -49,7 +49,7 @@ \itemV{12}{18}{x}{\Subs}{GAUT integration} GAUT release that interprets the task communication API. - \itemV{18}{24}{x}{\Subs}{GAUT integration} + \itemV{18}{27}{x}{\Subs}{GAUT integration} GAUT release that writes \xcoachplus format. - \itemL{24}{36}{x}{\Subs}{GAUT integration}{6:6:3} + \itemL{27}{36}{x}{\Subs}{GAUT integration}{6:6:3} \setMacroInAuxFile{gautFinal} GAUT release taking into account demonstrator's feedback. @@ -68,7 +68,7 @@ \itemV{0}{12}{d}{\Supmc}{Frequency calibration} A document describing the set up of the coprocessor frequency calibration. - \itemV{12}{24}{x}{\Supmc}{Frequency calibration} + \itemV{12}{27}{x}{\Supmc}{Frequency calibration} A VHDL description of hardware added to the coprocessor to enable the calibration. - \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{1:1:4} + \itemL{27}{33}{x}{\Supmc}{Frequency calibration}{1:1:4} \setMacroInAuxFile{freqCalibrationVhdl} The frequency calibration software consists of a driver in the FPGA-SoC operating @@ -78,5 +78,5 @@ \subtask{GAUT enhancement} \begin{livrable} - \itemV{18}{24}{d}{\Subs}{GAUT enhancement} + \itemV{18}{27}{d}{\Subs}{GAUT enhancement} Specification of GAUT enhancements. The first ones is to support new constraints and objectives. @@ -84,5 +84,5 @@ able to use synthesis feed-back informations in order to explore the design space and to generate optimized architectures. - \itemL{24}{36}{x}{\Subs}{GAUT enhancement}{0:4:4} + \itemL{27}{36}{x}{\Subs}{GAUT enhancement}{0:4:4} Integration of these enhancements into the final GAUT release ({\gautFinal} deliverable). Index: /anr/task-csg.tex =================================================================== --- /anr/task-csg.tex (revision 303) +++ /anr/task-csg.tex (revision 304) @@ -10,9 +10,10 @@ \begin{itemize} \item The development of the synthesizable models required for the connection - of the coprocessors on the platform bus (2 bridges). + of the coprocessors on the platform bus (2 bridges). \item The configuration and the development of drivers of the operating - systems (Board Support Package, HAL). + systems (Board Support Package, HAL). \item The CSG software that generates the SystemC simulators for prototyping - and the FPGA-SoC system including its bitstream and software executable code. + and the FPGA-SoC system including its bitstream and software executable code + (see Figure~\ref{architecture-csg} and ~\ref{architecture-hls}). \end{itemize} A first release will be delivered at $T0+12$ to allow the demonstrators to start working. @@ -24,15 +25,15 @@ \subtask{Bridge implementation} This \ST deals with the development of the synthesizable models required for - the connection of the coprocessors on the platform bus. + the connection of the coprocessors on the platform bus. \begin{livrable} - \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:2:5} + \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3} \setMacroInAuxFile{hpcPlbBridge} The synthesizable VHDL description of a PLB/VCI bridge. - \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:2:5} + \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3} \setMacroInAuxFile{hpcAvalonBridge} The synthesizable VHDL description of an AVALON/VCI bridge. \end{livrable} \subtask{OS setup} - This \ST consists of the configuration of the SocLib DNA operating + This \ST consists of the configuration of the SocLib DNA operating system and the development of drivers for the hardware architectural templates. For the \altera and \xilinx architectural templates, the OS must also be ported on @@ -62,13 +63,19 @@ architectural template, and an integration of an HLS tools but only for SystemC prototyping. - \itemV{18}{24}{x}{\Supmc}{CSG} + \itemV{18}{27}{x}{\Supmc}{CSG} This release extends CSG to FPGA-SoC generation for the \xilinx and - \altera architectural template. - \itemL{24}{36}{x}{\Supmc}{CSG tool}{5:3:2} - \OtherPartner{0}{36}{\Stima}{0:6:0} - \OtherPartner{0}{36}{\Smds}{0:6:0} - \setMacroInAuxFile{csgImplementation} - \mustbecompleted{TIMA : integration d'OS dans CSG, en particulier DNA} + \altera architectural template. + \itemL{27}{36}{x}{\Supmc}{CSG tool}{5:2:3} + \OtherPartner{0}{36}{\Stima}{1:3:2} + \OtherPartner{0}{36}{\Smds}{1:3:3} + \setMacroInAuxFile{csgImplementation} Final release of CSG enhanced by the demonstrator's feedback. + \\ + The work will be split between the partner as follow: 1) \Supmc will + design the core of CSG, 2) \Stima will design the part concerning the + generation of system software and the configuration of CSG to other OS. + 3) \Smds will focus to interface CSG to the IP-XACT format for + generating IP integrable into a IP-XACT flow such as socket and to + configure CSG to new IP or plate-form. \end{livrable} \end{workpackage} Index: /anr/task-demonstrator.tex =================================================================== --- /anr/task-demonstrator.tex (revision 303) +++ /anr/task-demonstrator.tex (revision 304) @@ -86,5 +86,5 @@ 3) the design time from a high level description. \begin{livrable} - \itemV{18}{24}{d+x}{\Smds}{Evaluation} + \itemV{18}{27}{d+x}{\Smds}{Evaluation} This deliverable written by \Smds, \Sbull and \Sthales is a document that synthesizes the results got for the demonstrators @@ -92,6 +92,6 @@ \NOVERStrtSpearde, \NOVERSmdsAppSpecification) using the COACH milestone of T0+18. - \itemV{24}{30}{d+x}{\Smds}{Evaluation} - Same as former but for the milestone of T0+24. + \itemV{27}{30}{d+x}{\Smds}{Evaluation} + Same as former but for the milestone of T0+27. \itemL{30}{36}{d+x}{\Smds}{Evaluation}{0:5:5} \OtherPartner{18}{36}{Sbull}{0:5:5} @@ -104,32 +104,4 @@ \NOVERStrtAppSpecification) will be provide. \end{livrable} -%% GROUPED ABOVE%% \begin{livrable} -%% GROUPED ABOVE%% \itemV{24}{30}{d+x}{\Smds}{\mds evaluation} -%% GROUPED ABOVE%% This deliverable is a document describing the result got for the application -%% GROUPED ABOVE%% (\mdsAppSpecification) using COACH milestone of T0+24. -%% GROUPED ABOVE%% \itemL{30}{36}{d+x}{\Smds}{\mds evaluation}{0:5:5} -%% GROUPED ABOVE%% This deliverable is a document that validates and evaluates COACH (final release) -%% GROUPED ABOVE%% for the \mds demonstrators (\mdsAppSpecification). -%% GROUPED ABOVE%% % -%% GROUPED ABOVE%% \itemV{24}{30}{d+x}{\Sbull}{\bull evaluation} -%% GROUPED ABOVE%% This deliverable is a document describing the result got for the application -%% GROUPED ABOVE%% (\bullAppSpecification) using COACH milestone of T0+24. -%% GROUPED ABOVE%% \itemL{30}{36}{d+x}{\Sbull}{\bull evaluation}{0:5:5} -%% GROUPED ABOVE%% This deliverable is a document that validates and evaluates COACH (final release) -%% GROUPED ABOVE%% for the \bull demonstrators (\bullAppSpecification). -%% GROUPED ABOVE%% % -%% GROUPED ABOVE%% \itemV{18}{24}{d+x}{\Sthales}{\thales evaluation} -%% GROUPED ABOVE%% This deliverable is a document describing the result got for the application -%% GROUPED ABOVE%% (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18. -%% GROUPED ABOVE%% The updated code of the application will be also provide. -%% GROUPED ABOVE%% \itemV{24}{30}{d+x}{\Sthales}{\thales evaluation} -%% GROUPED ABOVE%% This deliverable is a document describing the result got for the application -%% GROUPED ABOVE%% (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24. -%% GROUPED ABOVE%% The updated code of the application will be also provide. -%% GROUPED ABOVE%% \itemL{30}{36}{d+x}{\Sthales}{\thales evaluation}{0:5:5} -%% GROUPED ABOVE%% This deliverable is a document that validates and evaluates COACH (final release) -%% GROUPED ABOVE%% for the \thales demonstrators (\trtAppSpecification). -%% GROUPED ABOVE%% The updated code of the application will be also provide. -%% GROUPED ABOVE%% \end{livrable} \end{workpackage} Index: /anr/task-dissemination.tex =================================================================== --- /anr/task-dissemination.tex (revision 303) +++ /anr/task-dissemination.tex (revision 304) @@ -48,6 +48,6 @@ task graph can be obtained. \end{description} - \itemL{30}{36}{d}{\Supmc}{Tutorial}{1.5:0.0:1.5} - \OtherPartner{30}{36}{\Smds}{0:0:2} + \itemL{30}{36}{d}{\Supmc}{Tutorial}{1.5:0.0:1.0} + \OtherPartner{30}{36}{\Smds}{1.5:0:1} The final release of the tutorial. It will be completed with sections that illustrate: @@ -63,14 +63,14 @@ \subtask{Reference user manuals} \begin{livrable} - \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:1:0} + \itemL{21}{27}{d}{\Stima}{CSG User manual}{0:.5:1} This user manual shows how to generate a complete HW/SW system by using CSG tool. - \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:1:0} + \itemL{21}{27}{d}{\Slip}{HAS front-end user manual}{0:.5:1} This user manual shows how to apply loop transformations to a task. - \itemL{18}{36}{d}{\Sirisa}{ASIP user manual}{0:1:1} + \itemL{21}{27}{d}{\Sirisa}{ASIP user manual}{0:1:1} This user manual shows how to customize a processor to obtain an ASIP. - \itemL{18}{24}{d}{\Subs}{HLS user manual}{0:1:0} + \itemL{21}{27}{d}{\Subs}{HLS user manual}{0:.5:1} This user manual shows how a task can be synthesized by using UGH and GAUT tools. \OtherPartner{12}{36}{\Subs}{0:2:2} - \itemL{18}{36}{d}{\Smds}{Magillem framework user manual}{0:1:1} + \itemL{21}{27}{d}{\Smds}{Magillem framework user manual}{0:1:1} This user manual describes how to use COACH within the IP-XACT based Magillem tool suite. \end{livrable} Index: /anr/task-frontend.tex =================================================================== --- /anr/task-frontend.tex (revision 303) +++ /anr/task-frontend.tex (revision 304) @@ -31,5 +31,5 @@ custom instructions are specified by the user, and then automatically extracted (when beneficial) from the application intermediate representation. - \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0} + \itemL{18}{27}{x}{\Sirisa}{ASIP compilation flow}{0:6:3} In this second version, the software will also be able to automatically identify interesting pattern candidates in the application code, and use them as custom @@ -50,8 +50,8 @@ \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS} {A synthesizable VHDL model for a simple extensible MIPS architectural template} - \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0} + \itemL{18}{27}{h}{\Sirisa}{VHDL for extensible MIPS}{9:9:3} {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of its instruction set extensions} - \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2} + \itemL{27}{36}{d}{\Sirisa}{Evaluation report }{0:0:2} {An evaluation report with quantitative analysis of the performance/area trade-off induced by the different approaches} Index: /anr/task-hpc.tex =================================================================== --- /anr/task-hpc.tex (revision 303) +++ /anr/task-hpc.tex (revision 304) @@ -41,11 +41,13 @@ A library implementing the communication API defined in the {\hpcCommApi} deliverable. This library is dedicated to help the end-user to partition an application for HPC. - \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2:0} - \setMacroInAuxFile{hpcCommLinux} - The PC part of the HPC communication API that communicates with the FPGA-SOC, a - library and a LINUX module. - \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} - \setMacroInAuxFile{hpcDnaDriver} - The FPGA-SoC part of the communication API (DNA driver). + \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5} + \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0} + \OtherPartner{21}{27}{\Sbull}{0:0.5:0.5} + \setMacroInAuxFile{hpcForLinux} + This deliverable groups all the software components to implement the + HPC communication API (\NOVERShpcCommApi). + \Supmc will develop the Linux part (a C library and a LINUX module), + \Stima will develop the FPGA-SoC part (a DNA driver), + \Sbull will check this implementation on its demonstrator (\NOVERSbullAppSpecification). \end{livrable} % @@ -54,5 +56,5 @@ required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. \begin{livrable} - \itemL{12}{24}{h}{\Supmc}{PCI/X traffic generator}{0:1:0} + \itemL{21}{27}{h}{\Supmc}{PCI/X traffic generator}{0:1:1} The SystemC description of a component that generates PCI/X traffic. It is required to prototype FPGA-SoC dedicated to HPC. Index: /anr/task-management.tex =================================================================== --- /anr/task-management.tex (revision 303) +++ /anr/task-management.tex (revision 304) @@ -28,12 +28,12 @@ levels: progress monitoring, record keeping, meeting organization, review organization, the writing of the review reports. - \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5} - \OtherPartner{0}{36}{\Supmc} {.5:.5:.5} - \OtherPartner{0}{36}{\Subs} {.5:.5:.5} - \OtherPartner{0}{36}{\Stima} {.5:.5:.5} - \OtherPartner{0}{36}{\Slip} {.5:.5:.5} - \OtherPartner{0}{36}{\Sirisa} {.5:.5:.5} - \OtherPartner{0}{36}{\Sthales}{.5:.5:.5} - \OtherPartner{0}{36}{\Sbull} {.5:.5:.5} + \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5}% + \OtherPartner{0}{36}{\Supmc} {.5:.5:.5}% + \OtherPartner{0}{36}{\Subs} {.5:.5:.5}% + \OtherPartner{0}{36}{\Stima} {.5:.5:.5}% + \OtherPartner{0}{36}{\Slip} {.5:.5:.5}% + \OtherPartner{0}{36}{\Sirisa} {.5:.5:.5}% + \OtherPartner{0}{36}{\Sthales}{.5:.5:.5}% + \OtherPartner{0}{36}{\Sbull} {.5:.5:.5}% Project management at the partner level. It includes mainly the progress monitoring, the record keeping the participation to the project meetings