Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 306) +++ /anr/anr.tex (revision 307) @@ -2,5 +2,5 @@ \usepackage[french,english]{babel} -\usepackage[utf8x]{inputenc} +\usepackage[utf8]{inputenc} \usepackage{times} \usepackage[T1]{fontenc} Index: /anr/section-2.tex =================================================================== --- /anr/section-2.tex (revision 306) +++ /anr/section-2.tex (revision 307) @@ -33,30 +33,30 @@ communication infrastructure. \end{enumerate} -The proposed design flow starts from a high level description of the application, specified as a set of -parallel tasks written in C, without any assumption on the hardware or software implementation -of these tasks. It lets the system -designer in charge of expressing the coarse grain parallelism of the application, gives the designer -the possibility to explore various mapping of the application on the selected template architecture, -and offers a high predictability of results with respect to cost and performance objectives. -\\ -When this interactive, system level, design space exploration is completed (converging to -a specific mapping on a specific version of the selected architectural template), the rest of the flow -is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary -code for the software running on the embedded processors, and the bit-stream to program the target FPGA -will be automatically generated by the COACH tools. -% -\parlf -The strength of the COACH approach is the strong integration of the high-level synthesis tools -in a platform based design flow supporting virtual prototyping and design space exploration. -Most building blocks already exist (resulting from previous projects): the GAUT -or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology, -the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool, -as well as the SoCLib library of SystemC simulation models. -They must now be enhanced and integrated in a consistent design flow: this will -be done in Magillem framework thanks to the IP-XACT standard. -%The five academic laboratories worked very closely during more than one year (one monthly meeting -%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating -%those various technologies, and to define the detailed architecture of the proposed design flow. -%%% +%The proposed design flow starts from a high level description of the application, specified as a set of +%parallel tasks written in C, without any assumption on the hardware or software implementation +%of these tasks. It lets the system +%designer in charge of expressing the coarse grain parallelism of the application, gives the designer +%the possibility to explore various mapping of the application on the selected template architecture, +%and offers a high predictability of results with respect to cost and performance objectives. +%\\ +%When this interactive, system level, design space exploration is completed (converging to +%a specific mapping on a specific version of the selected architectural template), the rest of the flow +%is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary +%code for the software running on the embedded processors, and the bit-stream to program the target FPGA +%will be automatically generated by the COACH tools. +%% +%\parlf +%The strength of the COACH approach is the strong integration of the high-level synthesis tools +%in a platform based design flow supporting virtual prototyping and design space exploration. +%Most building blocks already exist (resulting from previous projects): the GAUT +%or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology, +%the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool, +%as well as the SoCLib library of SystemC simulation models. +%They must now be enhanced and integrated in a consistent design flow: this will +%be done in Magillem framework thanks to the IP-XACT standard. +%%The five academic laboratories worked very closely during more than one year (one monthly meeting +%%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating +%%those various technologies, and to define the detailed architecture of the proposed design flow. +%%%% \parlf In HPC (High Performance Computing), the targeted application is an existing one @@ -69,3 +69,8 @@ This will allow SMEs to enter HPC market for the applications that are unadapted to the current GPU based solutions. +\parlf +Coach generates SoC which is part of larger system. Thus it's important to take in account the existing industrial design flow. For this reason COACH will use the IP-XACT IEEE 1685 standard for packaging these generated SoC. +\begin{center}\begin{minipage}{.8\linewidth}\textit{ +The third objective of COACH is to facilitate the integration of generated SoC in global system design flow. +}\end{minipage}\end{center} %%% Index: /anr/section-consortium-desc.tex =================================================================== --- /anr/section-consortium-desc.tex (revision 306) +++ /anr/section-consortium-desc.tex (revision 307) @@ -169,5 +169,21 @@ \subsubsection{\mdslong} -\mustbecompleted{A COMPLETER: Emmanuel ....} +Magillem Design Services has been established by a team of seasoned engineers and a +group of business angels in the fall of 2006. The company has inherited Magillem, a +robust and innovative technology worth 120 man years. The Magillem environment is +dedicated to the design, verification and flow management of complex HW/SW based on IP-XACT. +In the service area, we audit the existing industrial flows and propose a work plan to +adapt them to IP-XACT, we validate and verify the full compatibility of tools interfaces +into a flow testbench, we test the IP deliverables against a benchmark for compliance +using our IP-XACT packager, and check IP integration properties onto a test system. +Magillem's tools are used in the most advanced production flows of integrated circuit +manufacturers (ST, NXP, TI, Qualcomm, etc.) and are linked with the research work of +the best laboratories of the domain (LIP6, TIMA, Fhg, OFFIS, etc.). Our participation +to leading European collaborative projects (e.g. IST COMPLEX, SPRINT, ICODES, etc.) +allow us to maintain a high level of innovation around our core technology: SoC design +methodologies at ESL, design and verification in AMS domain, HW/SW co-design, safety +and security of systems. +Beyond this core technology domain, Magillem has evolved with the tool suite called +Revenge, answering to wider assembly issues for large heterogeneous systems. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Index: /anr/section-consortium-leader.tex =================================================================== --- /anr/section-consortium-leader.tex (revision 306) +++ /anr/section-consortium-leader.tex (revision 307) @@ -3,3 +3,14 @@ coordonner le projet.} -\mustbecompleted{EMANNUEL} +Emmanuel Vaumorin is responsible for research and development program at MDS. Since 2003, +he is managing the realization of work for more than 12 projects (IST, MEDEA+, CATRENE, ANR, FUI, etc.). +Emmanuel is contributing member in the IP-XACT working group of ACCELERA. +In 2002-2005, Emmanuel was project manager of the project SystemC'mantic in +the former call RNTL. The main onjective was to set up a design and verification environment +based on the new language SystemC and introducing new techniques of system level design. +The partners of this project were Thales, CEA-LIST, TIMA, LESTER. +This project has reached all its objectives in time and has been well ranked by the reviewer. +In 2002-2003 he was product manager for an ESL design and verification +environment based on SystemC. Emmanuel is graduated from the Conservatoire +National des Arts et M\'etiers in the field of digital electronics for communications. +Emmanuel is one of the co-founders of Magillem. Index: /anr/section-consortium-people.tex =================================================================== --- /anr/section-consortium-people.tex (revision 306) +++ /anr/section-consortium-people.tex (revision 307) @@ -32,7 +32,8 @@ \peopletabularentry{\mds} -coordinator & Vaumorin & Emannuel & ... & ... & ... & ... \\\hline -... & ... & ... & ... & ... & ... & ... \\\hline - +coordinator & Vaumorin & Emannuel & Strategic Project Manager & ESL & ... & Project leader \\\hline +... & Spasevski & Cyril & CTO & EDA & ... & Technical specifications \\\hline +... & Guntz & St\'ephane & VP of Engineering & EDA & ... & Demonstrator specification and management \\\hline ... & Lucas & Ronan & & EDA & ... & Tools and demonstrator implementation \\\hline + \peopletabularentry{\irisa} ... & Derien & Steven & ... & ... & ... & ... \irisa \\\hline Index: /anr/section-etat-de-art.tex =================================================================== --- /anr/section-etat-de-art.tex (revision 306) +++ /anr/section-etat-de-art.tex (revision 307) @@ -221,4 +221,35 @@ an active research subject. +\subsubsection{SoC design flow automation using IP-XACT} + +IP-XACT is an XML based open standard defined by the Accellera consortium. +This non-profit organisation provides a unified set of high quality IP-XACT +specifications for documenting IP using meta-data. This meta-data will be +used for configuring, integrating, and verifying IP in advanced SoC design +and interfacing tools using TGI (Tight Generator Interface is a software API) +that can be used to access design meta-data descriptions of complete system designs. +The specification for the schema is tailored to the requirements of the industry, +and focused on enabling technologies for the efficient design of electronic +systems from concept to production. The last IEEE 1685 release of IP-XACT incorporates +both RTL and TLM (transaction level modelling) capabilities. Thus it can be used to +package IP portfolios and describe their assembly in complex hardware architectures. +These description files are the basis for tool interoperability and data exchange +through a common structured data management. Today more than two hundred companies +are members of the consortium and the board is incorporating top actors +(STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the +wide adoption by industry. Initiatives have already work for extending this standard +to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent +Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for +further releases. + +In IP-XACT the flow automation and data constistency is ensured by generators, which +are program modules that process IP-XACT XML data into something useful +for the design. They are key portable mechanism for encapsulating specialist design +knowledge and enable designers to deploy specialist knowledge in their design. It is +always possible to create generators in order to link several design or analysis tools +around a centric representation of metadata in IP-XACT. This kind of XML schema for +metadata management is a good solution for the federation of heterogeneous design domains +(models, tools, languages, methodologies, etc.). + %\subsubsection{High Performance Computing} %Accelerating high-performance computing (HPC) applications with field-programmable Index: /anr/section-issues.tex =================================================================== --- /anr/section-issues.tex (revision 306) +++ /anr/section-issues.tex (revision 307) @@ -6,6 +6,6 @@ indicateurs de réduction de coûts, perspectives de marchés (champs d’application, 
). Indicateurs des gains environnementaux, cycle de vie.} - - +% +\subsubsection*{Predominance of FPGA in the global electronic market} \begin{table}\leavevmode\center \begin{small}\begin{tabular}{|l|l|l|l|}\hline @@ -38,5 +38,6 @@ Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium volume markets. -\parlf +% +\subsubsection*{FPGAs and Embedded Systems} Today, FPGAs become important actors in the computational domain that was originally dominated by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed @@ -59,5 +60,5 @@ %This boosts the developpment of automatic design tools and methodologies. % -\parlf +\subsubsection*{FPGAs and High Performance Computing} Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand @@ -70,57 +71,21 @@ This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions is limited by the lack of design automation. -\\ -\\ +% +\subsubsection*{Evolution of architectures} +Nowadays processors mixing core and programmable matrix are available on the market (eg. Intel ATOM E600C). +"Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic +products (eg. PDAs and nomad items) and even personal computers. +To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools. + +% +\subsubsection*{COACH's contribution to this evolution} Nowadays, there are no commercial or academic tools covering the whole design flow from the system level specification to the bitstream generation neither for embedded system design nor for HPC. - -%PC => IA et Alain -%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue -%Je le mets donc en commentaire - -%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and -%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP, -%processor, bus core, ...) as well as incorporate their own IP. -%Designers can then generate a synthesized netlist, simulation test bench and custom -%software library that reflect the hardware configuration. -%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to -%simulate the platform at a high design level (systemC). -%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation -%tool to implement designs on \altera devices (Stratix, Arria, Cyclone). -%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize -%coprocessors from a C++ description. -%Nevertheless, they can only deal with data dominated applications and they do not handle -%the platform level. -%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to -%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs. -%Designers can design and simulate a system using MATLAB and Simulink. The tool will then -%automatically generate synthesizable Hardware Description Language (HDL) code mapped to -%\xilinx pre-optimized macro-cells. -%However, this tool targets only DSP based algorithms. -%\\ -%Consequently, a designer developping an embedded system needs to master four different -%design environments: -%\begin{enumerate} -% \item a virtual prototyping environment such as SoCLib for system level exploration, -% \item an architecture compiler (such as SOPC Builder from \altera, or System generator -% from \xilinx) to define the hardware architecture, -% \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for -% coprocessor synthesis, -% \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation. -%\end{enumerate} -%Furthermore, mixing these tools requires an important interfacing effort and this makes -%the design process very complex and achievable only by designers skilled in many domains. - \begin{center}\begin{minipage}{.9\linewidth}\textit{ The aim of the COACH project is to integrate all these design steps into a single design framework and to allow \textbf{pure software} developpers to design embedded systems. }\end{minipage}\end{center} - -%PC => IA et Alain -% le paragraphe suivant est coupé collé de la section suivante 2.2 - - -\parlf +% The COACH project proposes an open-source framework for mapping multi-tasks software applications on Field Programmable Gate Array circuits (FPGA). Index: /anr/section-position.tex =================================================================== --- /anr/section-position.tex (revision 306) +++ /anr/section-position.tex (revision 307) @@ -23,5 +23,5 @@ %on Field Programmable Gate Array circuits (FPGA). %%% -\parlf +\subsubsection*{Positionning in regards with the economical and social context} COACH will contribute to build an open design and run-time environment, including communication middleware and tools to support @@ -37,5 +37,6 @@ \item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive environment, suitable for co-operative and distributed development. -\item \mustbecompleted{IP-XACT: .... MAGILLEM...} +\item Integration of the solutions and engines being developped into a state of the art SoC and system +design flow, using the IP-XACT IEEE 1685 standard. \end{itemize} COACH outcome will contribute to strengthen Europe's competitive position by developing @@ -51,4 +52,5 @@ %%% \parlf\noindent +\subsubsection*{Positionning and continuity with other projects} The COACH project will benefit from a number of previous recent projects: \begin{description} @@ -88,7 +90,22 @@ CAIRN group in the context of the ANR BioWic project (2009-2011), so as to be able to validate the framework on real-life HPC applications. - \item[SoCket] \mustbecompleted{...... MAGILEM ......} - \item[HOSPI] \mustbecompleted{...... MAGILEM ......} - \item[SoftSoc] \mustbecompleted{...... MAGILEM ......} + + \item[SoCket] + The design flow defined in this project targets the design of critical embedded systems. + It covers important steps as system architecture exploration, and the definition of virtual + prototypes at different levels of abstraction to support early embedded software development, + verification of hardware blocks, and preparation of certification activities. + COACH solutions and engines will be specified to be integrated into this standard flow. + MDS, Thales TRT, TIMA are already collaborating in this project. + + \item[HOSPI] + The objective of this project (with TIMA and MDS) was to define innovative methods, and implement the associated tools, to ease + the mapping of data-streaming applications on heterogeneous platforms. COACH will use the abstracted description + format based on IP-XACT for hardware platforms and the results concerning the integration of code generators into a standard design flow. + + \item[SoftSoC] + TIMA and MDS are involved in this project, which aims at the standard definition and generation of Hardware Dependent Software layers of a system. + Crucial extensions of the IP-XACT standard will be reused from this project, as well as code generation techniques based on them. + \end{description} %%% @@ -125,8 +142,13 @@ will be very useful as a front-end for HLS tools. \item - Regarding \mustbecompleted{.... MAGILLEM ... IP-XACT} + Regarding industrial flow integration \mds will bring its strong expertise + in IEEE 1685 (IP-XACT) standard. \mds team is involved and contributes actively + to it since 2003 and Magillem tool suite is used for its validation. Magillem is used in + industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales, + Astrium, Thomson, etc. what guarantees a strong alignement on customers needs and enhance results exploitation. + \end{itemize} %%% -\parlf\noindent +\subsubsection*{Relevance to the call axis} The COACH project totally fulfills the objectives of the axis 2 "METHODES, OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES". @@ -163,5 +185,7 @@ quality and reducing the design time and the cost of synthesised cryptographic devices. \mustbecompleted{END-FIXME} -\parlf +% +\subsubsection*{European and international positionning} +% Finally, it is worth to note that this project covers priorities defined by the commission experts in the field of Information Technolgies Society (IST) for Embedded Index: /anr/task-demonstrator.tex =================================================================== --- /anr/task-demonstrator.tex (revision 306) +++ /anr/task-demonstrator.tex (revision 307) @@ -71,9 +71,26 @@ % \subtask{\mds use case} - \mustbecompleted{\mds will use .................} + The goal of the \mds demonstrator will be to experiment and validate the good integration + of the COACH tools into an industrial SoC design flow for critical systems. This demonstrator will be based on + the standard flow defined in the SoCket project and \mds will use a classical SoC platform + based on the LEON processor and which simulation models are available for free (this will + facilitate the further dissemination of the demonstrators to external prospects). + The required prototypes of IP-XACT generators will be specified and implemented; they will be + generic enough or at least customizable in order to be at the basis of the further deployement into + actual design flows. The objectives of this demonstrator are the following: +\begin{itemize} + \item Validate the IP-XACT packaging of the generated SoC + \item Experiment the integration of the generated SoC into the top level (TLM or RTL) of a bigger system + \item Bring a focus on flow capabilities for requirements traceability from system properties, down to sub-systems implementation +\end{itemize} + \begin{livrable} - \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0} + \itemL{0}{12}{d}{\Smds}{Use case}{6:7:0} \setMacroInAuxFile{mdsAppSpecification} - \mustbecompleted{Adaptation of ...} + This deliverable is a document that specifies the demonstrator. + \itemL{12}{24}{x}{\Smds}{\mds demonstrator}{4:0:0} + This deliverable is the intermediate demonstrator specified in (\mdsAppSpecification). + \itemL{24}{12}{x}{\Smds}{\mds demonstrator}{4:0:0} + This deliverable is the final demonstrator specified in (\mdsAppSpecification). \end{livrable}