Index: anr/section-2.tex
===================================================================
--- anr/section-2.tex	(revision 297)
+++ anr/section-2.tex	(revision 307)
@@ -33,30 +33,30 @@
       communication infrastructure.
 \end{enumerate}
-The proposed design flow starts from a high level description of the application, specified as a set of 
-parallel tasks written in C, without any assumption on the hardware or software implementation
-of these tasks. It lets the system
-designer in charge of expressing the coarse grain parallelism of the application, gives the designer
-the possibility to explore various mapping of the application on the selected template architecture,
-and offers a high predictability of results with respect to cost and performance objectives.
-\\
-When this interactive, system level, design space exploration is completed (converging to
-a specific mapping on a specific version of the selected architectural template), the rest of the flow 
-is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
-code for the software running on the embedded processors, and the bit-stream to program the target FPGA 
-will be automatically generated by the COACH tools.
-%
-\parlf
-The strength of the COACH approach is the strong integration of the high-level synthesis tools 
-in a platform based design flow supporting virtual prototyping and design space exploration.
-Most building blocks already exist (resulting from previous projects): the GAUT 
-or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
-the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
-as well as the SoCLib library of SystemC simulation models.
-They must now be enhanced and integrated in a consistent design flow: this will
-be done in Magillem framework thanks to the IP-XACT standard.
-%The five academic laboratories worked very closely during more than one year (one monthly meeting
-%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
-%those various technologies, and to define the detailed architecture of the proposed design flow.
-%%%
+%The proposed design flow starts from a high level description of the application, specified as a set of 
+%parallel tasks written in C, without any assumption on the hardware or software implementation
+%of these tasks. It lets the system
+%designer in charge of expressing the coarse grain parallelism of the application, gives the designer
+%the possibility to explore various mapping of the application on the selected template architecture,
+%and offers a high predictability of results with respect to cost and performance objectives.
+%\\
+%When this interactive, system level, design space exploration is completed (converging to
+%a specific mapping on a specific version of the selected architectural template), the rest of the flow 
+%is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
+%code for the software running on the embedded processors, and the bit-stream to program the target FPGA 
+%will be automatically generated by the COACH tools.
+%%
+%\parlf
+%The strength of the COACH approach is the strong integration of the high-level synthesis tools 
+%in a platform based design flow supporting virtual prototyping and design space exploration.
+%Most building blocks already exist (resulting from previous projects): the GAUT 
+%or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
+%the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
+%as well as the SoCLib library of SystemC simulation models.
+%They must now be enhanced and integrated in a consistent design flow: this will
+%be done in Magillem framework thanks to the IP-XACT standard.
+%%The five academic laboratories worked very closely during more than one year (one monthly meeting
+%%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
+%%those various technologies, and to define the detailed architecture of the proposed design flow.
+%%%%
 \parlf
 In HPC (High Performance Computing), the targeted application is an existing one
@@ -69,3 +69,8 @@
 This will allow SMEs to enter HPC market for the applications that are
 unadapted to the current GPU based solutions.
+\parlf
+Coach generates SoC which is part of larger system. Thus it's important to take in account the existing industrial design flow. For this reason COACH will use the IP-XACT IEEE 1685 standard for packaging these generated SoC.
+\begin{center}\begin{minipage}{.8\linewidth}\textit{
+The third objective of COACH is to facilitate the integration of generated SoC in global system design flow.
+}\end{minipage}\end{center}
 %%%
