Index: /anr/anr.bib
===================================================================
--- /anr/anr.bib	(revision 312)
+++ /anr/anr.bib	(revision 313)
@@ -1,26 +1,43 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 %%%%% MDS
-@inproceedings{mds:2008,
- author = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin, Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe, de Paoli Serge and Vaumorin Emmanuel},
- title = {Industrial IP integration flows based on IP-XACT standards},
- booktitle = {Proceedings of the conference on Design, automation and test in Europe},
- series = {DATE '08},
- year = {2008},
- isbn = {978-3-9810801-3-1},
- location = {Munich, Germany},
- pages = {32--37},
- numpages = {6},
- url = {http://doi.acm.org/10.1145/1403375.1403386},
- doi = {http://doi.acm.org/10.1145/1403375.1403386},
- acmid = {1403386},
- publisher = {ACM},
- address = {New York, NY, USA},
+%Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe,
+%de Paoli Serge and Vaumorin Emmanuel
+@inproceedings{mds1,
+  author    = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin and All},
+  title     = {Industrial IP integration flows based on IP-XACT standards},
+  booktitle = {Proceedings of the conference on Design, automation and test in Europe},
+  series    = {DATE'08},
+  year      = {2008},
+  isbn      = {978-3-9810801-3-1},
+  location  = {Munich, Germany},
+  pages     = {32--37},
+  numpages  = {6},
+  url       = {http://doi.acm.org/10.1145/1403375.1403386},
+  doi       = {http://doi.acm.org/10.1145/1403375.1403386},
+  acmid     = {1403386},
+  publisher = {ACM},
+  address   = {New York, NY, USA},
 } 
 
-@report{rapportministere,
- author = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
- title = {Briques g\'en\'eriques du logiciel embarqu\'e},
- year = {2010},
- publisher = {Mininist\'ere de l'industrie},
+@misc{mds2,
+  author       = {E. Vaumorin, M. Palus, F. Clermidy and J. Martin},
+  title        = {SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform},
+  howpublished = {\url{http://www.design-reuse.com/articles/18613/ip-xact-esl-noc.html}},
+  year         = {2008},
+}
+
+@misc{socketflow,
+  author       = {L. Maillet-Contoz, R. Lucas and E. Vaumorin},
+  title        = {SocKET design flow and Application on industrial use cases},
+  howpublished = {\url{http://socket.imag.fr/Presentations-socket/Vendredi15/Presentation_flot.pdf}},
+  note         = {home site: \url{http://socket.imag.fr/}},
+  year         = {2010},
+}
+
+@techreport{rapport-ministere,
+ author      = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
+ title       = {Briques g\'en\'eriques du logiciel embarqu\'e},
+ year        = {2010},
+ institution = {Mininist\'ere de l'industrie},
 }
 
@@ -199,14 +216,14 @@
 
 
-@INBOOK{HLSBOOK,
+@BOOK{HLSBOOK,
   author    = {P. Coussy and A. Morawiec},
-  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
+  title = {High-Level Synthesis: From Algorithm to Digital Circuits},
   publisher = {Springer},
   year      = {2008},
 }
 
-@INBOOK{CATRENE,
+@BOOK{CATRENE,
   author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
-  booktitle = {European Roadmap for EDA},
+  title = {European Roadmap for EDA},
   publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
   year      = {2009},
Index: /anr/section-etat-de-art.tex
===================================================================
--- /anr/section-etat-de-art.tex	(revision 312)
+++ /anr/section-etat-de-art.tex	(revision 313)
@@ -226,4 +226,7 @@
 \subsubsection{SoC design flow automation using IP-XACT}
 \label{soa:ip-xact}
+% EV: Industrial IP integration flows based on IP-XACT standards: \cite{mds1}\\
+% EV: SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform: \cite{mds2}\\
+% EV: SocKET design flow and Application on industrial use cases: \cite{socketflow}\\
 IP-XACT is an XML based open standard defined by the Accellera consortium. 
 This non-profit organisation provides a unified set of high quality IP-XACT 
Index: /anr/section-objectif.tex
===================================================================
--- /anr/section-objectif.tex	(revision 312)
+++ /anr/section-objectif.tex	(revision 313)
@@ -112,4 +112,4 @@
 \\
 The framework functionalities will be demonstrated with the demonstrators
-(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
-page~\ref{subtask-tutorial}).
+(see task-7 page~\pageref{task-demonstrator}) and the tutorial example (see task-8
+page~\pageref{subtask-tutorial}).
Index: /anr/task-csg.tex
===================================================================
--- /anr/task-csg.tex	(revision 312)
+++ /anr/task-csg.tex	(revision 313)
@@ -15,5 +15,5 @@
   \item The CSG software that generates the SystemC simulators for prototyping
     and the FPGA-SoC system including its bitstream and software executable code
-    (see Figure~\ref{architecture-csg} and ~\ref{architecture-hls}).
+    (see Figure~\ref{archi-csg} and ~\ref{archi-hls}).
 \end{itemize}
 A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
Index: /anr/task-demonstrator.tex
===================================================================
--- /anr/task-demonstrator.tex	(revision 312)
+++ /anr/task-demonstrator.tex	(revision 313)
@@ -1,2 +1,3 @@
+\label{task-demonstrator}
 \begin{taskinfo}
 \let\MDS\enable