Index: /anr/section-etat-de-art.tex =================================================================== --- /anr/section-etat-de-art.tex (revision 338) +++ /anr/section-etat-de-art.tex (revision 339) @@ -44,5 +44,5 @@ researches on HPC-FPGA are mainly conducted in the USA. None of the approaches developed in these researches are fulfilling entirely the -challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator, +challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in an FPGA accelerator, but extension generation is not automated and requires hardware design skills. Mitrionics has an elegant solution based on a compute engine specifically @@ -74,9 +74,9 @@ tool will then automatically generate synthesizable Hardware Description Language (HDL) code mapped to \xilinx pre-optimized algorithms. -However, this tool targets only DSP based algorithms, \xilinx FPGAs and +However, this tool targets onlysignal processing algorithms, \xilinx FPGAs and cannot handle a complete SoC. Thus, it is not really a system synthesis tool. \\ In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx -Platform Studio XPS from \xilinx allows to describe a system, to synthesize it, +Platform Studio XPS from \xilinx allow to describe a system, to synthesize it, to program it into a target FPGA and to upload a software application. Both SOPC Builder and XPS, allow designers to select and parameterize components from @@ -126,5 +126,5 @@ Low power consumption constraint which is mandatory for embedded systems is not yet well handled or not handled at all by the HLS tools already available, -\item The parallelism is extracted from initial specification. +\item The parallelism is extracted from the initial specification. To get more parallelism or to reduce the amount of required memory in the SoC, the user must re-write the algorithmic specification while there are techniques such as polyedric @@ -166,5 +166,5 @@ This approach however has a severe weakness, since it also significantly reduces opportunities for achieving good speedups (most speedups remain between 1.5x and -2.5x), since ISEs performance is generally tied down by I/O constraints as +2.5x), since ISEs performance is generally limited by I/O constraints as they generally rely on the main CPU register file to access data. @@ -219,5 +219,5 @@ As a side effect, it has been observed that the polyhedral model is a useful tool for many other optimization, like memory reduction and locality -improvement. Another point is +improvement. Itshould be noted that the polyhedral model \emph{stricto sensu} applies only to very regular programs. Its extension to more general programs is @@ -245,7 +245,7 @@ are members of the consortium and the board is incorporating top actors (STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the -wide adoption by industry. Initiatives have already% work for (paul) +wide adoption by industry. Initiatives have already attempted to extend this standard -to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent +to the AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for further releases. Index: /anr/section-issues.tex =================================================================== --- /anr/section-issues.tex (revision 338) +++ /anr/section-issues.tex (revision 339) @@ -27,7 +27,7 @@ \end{table} % -Microelectronic components allow the integration of complex functions into products, increases +Microelectronic components allow integration of complex functions into products, increases commercial attractivity of these products and improves their competitivity. -\cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 minimum. +\cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 at least. Multimedia and communication sectors have taken advantage from microelectronics facilities thanks to the developpment of design methodologies and tools for embedded systems. @@ -36,12 +36,12 @@ An IC foundry costs several billions of euros and the fabrication of a specific circuit costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 -million USD. Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium -volume markets and the new trend for building the new generation products will be multi processors SoCs and programmable logic for co-processsing. +million \$ . Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium +volume markets and the new trend for building the new generation products will be multi processors SoCs and +programmable logic for co-processsing. \\ -According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), the global growth is 30 Billons\$ between 2009-2013 for multimedia and communication sectors; this is 6 times more than all other domains like security, home automation, health. -The predominance%paul -the multimedia and communication sectors -%results paul -are due to their being predominently a mass market. +According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), +the global growth is 30 billon\$ between 2009-2013 for the multimedia and communication sectors; this is +6 times more than all other domains like security, home automation or health. +The predominance of the multimedia and communication sectors are due to their being predominently a mass market. % \subsubsection*{FPGAs and Embedded Systems} @@ -82,5 +82,6 @@ Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic products (eg. PDAs and nomad items) and even personal computers. -To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools. +To take benefit of such architectures, developping and deploying application will require innovative +codesign methods and tools. % @@ -96,5 +97,5 @@ The COACH project proposes an open-source framework for mapping multi-tasks software applications on Field Programmable Gate Array circuits (FPGA). -It aims to propose solutions to the societal/economical challenges by +Its aim is to propose solutions to the societal/economical challenges by providing SMEs novel design capabilities enabling them to increase their design productivity with design exploration and synthesis methods that are placed on top @@ -109,4 +110,5 @@ to launch start-ups in software engineering. \\ -So this may increase the total%amount (paul) -number of engineers working in this domain: today in France the total is only 26,000 of which 16,000 are in big companies \cite{rapport-ministere}. +So this may increase the total +number of engineers working in this domain: today in France the total is only 26,000 of which +16,000 are in big companies \cite{rapport-ministere}. Index: /anr/section-position.tex =================================================================== --- /anr/section-position.tex (revision 338) +++ /anr/section-position.tex (revision 339) @@ -40,5 +40,5 @@ design flow, using the IP-XACT IEEE 1685 standard \end{itemize} -COACH outcome will contribute to strengthen Europe's competitive position by developing +The COACH results will contribute to strengthen Europe's competitive position by developing technologies and methodologies for product design, focusing (in compliance with the %scope of the above program) on technologies, engineering methodologies, novel tools, @@ -68,5 +68,5 @@ proposes to develop a reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its computing - structure to computation patterns that can be speed-up and/or + structure to computation patterns that can be faster or more power efficient. %The ROMA project study a pipeline of %evolved low-power coarse grain reconfigurable operators to avoid @@ -152,5 +152,6 @@ \subsubsection*{Relevance to the call axis} This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing -methods and tools for the design of application to be run on platforms of the next generation. Results will be gained in term of productivity, +methods and tools for the design of application to be run on platforms of the next generation. +Inprovements can be expected for productivity, time-to-market (automation and code generation) and safety (management of high level sepcifications down to implementation). In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES, @@ -182,6 +183,6 @@ % The results of the COACH project will help users to build cryptographic secure systems implemented in -hardware or both in software/hardware in an effective way, substantially enhancing the -process productivity of the cryptographic algorithms hardware synthesis, improving the +in a combination of hardware and software in an effective way, substantially enhancing the +productivity of the field, improving the quality and reducing the design time and the cost of synthesised cryptographic devices. %