Changeset 353 for anr


Ignore:
Timestamp:
Feb 4, 2011, 2:04:42 AM (14 years ago)
Author:
coach
Message:

Presque 40 pages.

Location:
anr
Files:
6 edited

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  • anr/anr.tex

    r352 r353  
    3434    \def\note#1{\marginnote{#1}\label{note:#1}}
    3535    \def\seenote#1{#1 (page~\pageref{note:#1})\xspace}
     36%\usepackage{array}
    3637\usepackage{anr}
    3738
    … …  
    282283\newpage\section{Staff involvement in other contracts}\input{annexe-autre-participation.tex}
    283284
     285\newpage\section{Man power by partners and by deliverables}
     286  \subsection{Partner 1: \mds}   \label{table-livrables-mds}   \input{table_mds_full.tex}
     287  \subsection{Partner 2: \upmc}  \label{table-livrables-upmc}  \input{table_upmc_full.tex}
     288  \subsection{Partner 3: \ubs}   \label{table-livrables-usb}   \input{table_ubs_full.tex}
     289  \subsection{Partner 4: \lip}   \label{table-livrables-lip}   \input{table_inria_compsys_full.tex}
     290  \subsection{Partner 5: \tima}  \label{table-livrables-tima}  \input{table_tima_full.tex}
     291  \subsection{Partner 6: \inria} \label{table-livrables-inria} \input{table_inria_cairn_full.tex}
     292  \subsection{Partner 7: \bull}  \label{table-livrables-bull}  \input{table_bull_full.tex}
     293  \subsection{Partner 8: \thales}\label{table-livrables-thales}\input{table_thales_full.tex}
     294
    284295\newpage\section{Effort tables}
    285296%\begin{small}

  • anr/section-1.tex

    r337 r353  
    1 % les objectifs globaux,
    2 The market of digital systems is about 4,600 M\$ today and is estimated to
    3 5,600 M\$ in 2012. However the ever growing application complexity involves
    4 integration of heterogeneous technologies and requires the design of
    5 complex Multi-Processors System on Chip (MPSoC).
    6 \\
    7 During the last decade, the use of ASICs (Application Specific
    8 Integrated Circuits) appeared to be more and more reserved to high volume markets, because
    9 the design and fabrication costs of such components exploded, due to increasing NRE (Non
    10 Recurring-Engineering) costs.
    11 Fortunately, FPGA (Field Programmable Gate Array) components, such as the
    12 Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
    13 implement a complete MPSoC with multiple processors and several dedicated
    14 coprocessors for a few Keuros per device.
    15 \\
    16 Many applications are initially captured
    17 algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
    18 in tools that can provide an implementation path directly from HLLs to hardware.
    19 Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
    20 Co-design, High-Level Synthesis...) are now mature and allow the automation of
    21 a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
    22 on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
    23 However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
    24 methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
    25 designs written in the C/C++ language and implementing the function directly into FPGA.
    26 We believe that coupling FPGA technologies and ESL methodologies
    27 will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
    28 devices and to enter new, low and medium volume markets.
    29 Furthermore, today there is an increasing industrial interest into IC
    30 that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
    31 such as the ATOM E600C chip (Intel).
    32 In few a years, one can expect that such chips will become current. Even standard
    33 general purpose CPU cores will contains a configurable area
    34 bringing an explosion in low and medium volume markets.
     1The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs (Application Specific Integrated Circuits) appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
    352\parlf
    36 The objective of COACH is to provide an integrated design flow for the design of
    37 multi-processors digital systems targeting FPGA devices.
    38 It will be dedicated to system/software designers, and hide as much as possible
    39 the hardware characteristics to the end-user.
    40 COACH will mainly target three kinds of digital systems:
    41 1) embedded and autonomous application such as  personal digital assistants (PDA),
    42    ambient computing components, or wireless sensor networks (WSN);
    43 2) PCI/E extension boards connected to a PC to accelerate a specific application,
    44    it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
    45 3) sub-system application for generating an IP to a larger system.
    46 \parlf
    47 %verrous scientifiques et techniques
    48 The COACH environment will integrate several hardware and software technologies:
    49 \begin{description}
    50 \item[Design Space Exploration:]
    51     The COACH environment will allow to describe an application as a process
    52         network i.e. a set of tasks communicating through FIFO channels.
    53         COACH will allow to map the application on a shared-memory, MPSoC architecture.
    54     It will permit to easily explore the design space to help the system designer
    55         to define the proper hardware/software partitioning of the application.
    56     For each point in the design space, metrics such as throughput, latency, power
    57     consumption, silicon area, memory allocation and data locality will be provided.
    58 \item[Hardware Accelerators Synthesis (HAS):]
    59     COACH will allow the automatic generation of hardware accelerators when required.
    60     Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
    61     (ASIP) design environments and source-level transformation tools (loop transformations
    62     and memory optimization) will be provided.
    63     This will allow further exploration of the micro-architectural design space.
    64     HLS tools are sensitive to the coding style of the input specification and the domain
    65     they target (control vs. data dominated).
    66     The HLS tools of COACH will support a common language and coding style to avoid
    67     re-engineering by the designer.
    68 \item[Platform based design:]
    69     COACH will handle both \altera and \xilinx FPGA devices.
    70     COACH will define architectural templates that can be customized by adding
    71     dedicated coprocessors and ASIPs and by fixing template parameters such as
    72     the number of embedded processors, the number and size of embedded memory banks
    73     or the embedded operating system.
    74     However, the specification of the application will be independent of both the
    75     architectural template and the target FPGA device.
    76     Basically, the following three architectural templates will be provided:
    77     \begin{enumerate}
    78     \item A Neutral architectural template based on the SoCLib IP core library and the
    79       VCI/OCP communication infrastructure.
    80     \item An \altera architectural template based on the \altera IP core library, the
    81       AVALON system bus and the NIOS processor.
    82     \item A \xilinx architectural template based on the \xilinx IP core library,
    83       the \xilinxbus system bus and the \xilinxcpu processor.
    84     \end{enumerate}
    85 \item[Hardware/Software communication middleware:]
    86     COACH will implement an homogeneous HW/SW communication infrastructure and
    87     communication APIs (Application Programming Interface), that will be used for
    88     communications between software tasks running on embedded processors and
    89     dedicated hardware coprocessors.
    90 \item[Interaction with the industrial world:]
    91     COACH will not be a closed framework but it will be opened to the industrial
    92     world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
    93     architectural template and by providing the IP-XACT description of the generated MPSoC.
    94     This should facilitate the enhancement of the architectural template with IP and the
    95     integration of the IP produced by COACH in larger design.
    96 \end{description}
    97 %From the end user point of view, the specification of the application will be
    98 %independant from both the architectural template and from the selected FPGA
    99 %family.
    100 \parlf
    101 % le programme de travail
    102 %The COACH project targets fundamental issues related to design methodologies for
    103 %digital systems by providing estimation, exploration and design tools targeting both
    104 %performance and power optimization at all the abstraction levels of the flow (system,
    105 %architecture, algorithm and logic).
    106 To reach this ambitious goal, the project will rely on the experience and the
    107 %complementariness
    108 synergy of the partners in the following domains:
    109 Operating system and communication middleware (\tima, \upmc),
    110 MPSoC architectures (\tima, \ubs, \upmc),
    111 ASIP architectures (\inria),
    112 High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
    113 HPC (\bull, \thales, \lip), tools integration in IP-XACT flow (\mds).
    114 \\
    115 The COACH project does not start from scratch.
    116 It relies
    117 on the Magillem industrial platform for the integration into IP-XACT flows,
    118 on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
    119 on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
    120 on the ROMA~\cite{roma, RAFFIN:2010:INRIA-00539874:1} project for ASIP,
    121 on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
    122 transformations,
    123 and on the \xilinx and \altera IP core libraries.
    124 Finally it will use the \xilinx and \altera logic and physical synthesis tools
    125 to generate the FPGA configuration bitstreams.
    126 %The main development steps of the COACH project are:
    127 %\begin{enumerate}
    128 %   \item Definition of the end user inputs:
    129 %    The coarse grain parallelism of the application will be described as a communicating
    130 %    task graph, each task being described in C language.
    131 %    Similarly the architectural templates with their parameters and the design constraints
    132 %    will be specified.
    133 %  \item Definition of an internal format for representing task.
    134 %  \item Development of the GCC pluggin for generating the internal format of a
    135 %    C task.
    136 %  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
    137 %    the internal format. This will allow to swap from one tool to another one, and to
    138 %    chain them if necessary.
    139 %  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
    140 %    platform to generate the bitstream for the various FPGA families and architectural
    141 %    templates.
    142 %  \item Development of new tools such as ASIP compiler, HPC design environment and
    143 %    dynamic reconfiguration of FPGA devices.
    144 %\end{enumerate}
    145 \parlf
    146 The role of the industrial partners \bull, \thales and \mds is to provide
    147 real use cases to benchmark the COACH design environment and to analyze the designer productivity
    148 improvements.
    149 \parlf
    150 The COACH project will deliver an open and freely distributed infrastructure.
    151 The architectural templates and most of the software tools will be distributed under the
    152 GPL-like license.
    153 The VHDL synthesizable models for the neutral architectural template
    154 will also be freely available for non commercial use.
    155 For industrial exploitation the technology providers are ready to propose commercial licenses,
    156 directly to the end user, or through a third party.
    157 \parlf
     3Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow. Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both Small and Medium Enterprise and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest to IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. Probably in few years, such chips will become current and even standard general purpose CPU cores will contains a configurable area making explode the low and medium volume markets of digital systems. COACH’s objective is to provide an integrated design flow for the design of multi-processors digital systems targeting FPGA devices. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application such as personal digital assistants (PDA), ambient computing components, or wireless sensor networks, 2/ PCI-E extension boards connected to a PC to accelerate a specific application, it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing, 3/ Sub-system application for generating an IP to a larger system. The COACH open-source environment will integrate several hardware and software technologies:
     4%
     5\begin{itemize}
     6\item Design Space Exploration by allowing to describe an application as a process network i.e. a set of tasks communicating through FIFO channels and to map the application on a shared-memory, MPSoC architecture.
     7\item Hardware Accelerators Synthesis by allowing the automatic generation of hardware accelerators when required
     8\item Platform based design: three architectural templates will be provided (free-generic and ALTERA and XILINX’s IPs based).
     9\item Hardware/Software communication middleware by implementing an homogeneous HW/SW communication infrastructure and communication APIs (Application Programming Interface), that will be used for communications between software tasks running on embedded processors and dedicated hardware coprocessors.
     10\item Interaction with the industrial world: the framework will be open to the industrial world by using IP-XACT standard for describing the components of the architectural template and by providing the IP-XACT description of the generated MPSoC.
     11\end{itemize}
     12%
    15813\mustbecompleted{LIST NON A JOUR}
    15914The major FPGA companies (\xilinx and \altera) have expressed their interest for
    … …  
    16419ABOUND Logic, EADS-ASTRIUM.
    16520
     21%% % les objectifs globaux,
     22%% The market of digital systems is about 4,600 M\$ today and is estimated to
     23%% 5,600 M\$ in 2012. However the ever growing application complexity involves
     24%% integration of heterogeneous technologies and requires the design of
     25%% complex Multi-Processors System on Chip (MPSoC).
     26%% \\
     27%% During the last decade, the use of ASICs (Application Specific
     28%% Integrated Circuits) appeared to be more and more reserved to high volume markets, because
     29%% the design and fabrication costs of such components exploded, due to increasing NRE (Non
     30%% Recurring-Engineering) costs.
     31%% Fortunately, FPGA (Field Programmable Gate Array) components, such as the
     32%% Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
     33%% implement a complete MPSoC with multiple processors and several dedicated
     34%% coprocessors for a few Keuros per device.
     35%% \\
     36%% Many applications are initially captured
     37%% algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
     38%% in tools that can provide an implementation path directly from HLLs to hardware.
     39%% Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
     40%% Co-design, High-Level Synthesis...) are now mature and allow the automation of
     41%% a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
     42%% on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
     43%% However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
     44%% methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
     45%% designs written in the C/C++ language and implementing the function directly into FPGA.
     46%% We believe that coupling FPGA technologies and ESL methodologies
     47%% will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
     48%% devices and to enter new, low and medium volume markets.
     49%% Furthermore, today there is an increasing industrial interest into IC
     50%% that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
     51%% such as the ATOM E600C chip (Intel).
     52%% In few a years, one can expect that such chips will become current. Even standard
     53%% general purpose CPU cores will contains a configurable area
     54%% bringing an explosion in low and medium volume markets.
     55%% \parlf
     56%% The objective of COACH is to provide an integrated design flow for the design of
     57%% multi-processors digital systems targeting FPGA devices.
     58%% It will be dedicated to system/software designers, and hide as much as possible
     59%% the hardware characteristics to the end-user.
     60%% COACH will mainly target three kinds of digital systems:
     61%% 1) embedded and autonomous application such as  personal digital assistants (PDA),
     62%%    ambient computing components, or wireless sensor networks (WSN);
     63%% 2) PCI/E extension boards connected to a PC to accelerate a specific application,
     64%%    it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
     65%% 3) sub-system application for generating an IP to a larger system.
     66%% \parlf
     67%% %verrous scientifiques et techniques
     68%% The COACH environment will integrate several hardware and software technologies:
     69%% \begin{description}
     70%% \item[Design Space Exploration:]
     71%%     The COACH environment will allow to describe an application as a process
     72%%      network i.e. a set of tasks communicating through FIFO channels.
     73%%      COACH will allow to map the application on a shared-memory, MPSoC architecture.
     74%%     It will permit to easily explore the design space to help the system designer
     75%%      to define the proper hardware/software partitioning of the application.
     76%%     For each point in the design space, metrics such as throughput, latency, power
     77%%     consumption, silicon area, memory allocation and data locality will be provided.
     78%% \item[Hardware Accelerators Synthesis (HAS):]
     79%%     COACH will allow the automatic generation of hardware accelerators when required.
     80%%     Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
     81%%     (ASIP) design environments and source-level transformation tools (loop transformations
     82%%     and memory optimization) will be provided.
     83%%     This will allow further exploration of the micro-architectural design space.
     84%%     HLS tools are sensitive to the coding style of the input specification and the domain
     85%%     they target (control vs. data dominated).
     86%%     The HLS tools of COACH will support a common language and coding style to avoid
     87%%     re-engineering by the designer.
     88%% \item[Platform based design:]
     89%%     COACH will handle both \altera and \xilinx FPGA devices.
     90%%     COACH will define architectural templates that can be customized by adding
     91%%     dedicated coprocessors and ASIPs and by fixing template parameters such as
     92%%     the number of embedded processors, the number and size of embedded memory banks
     93%%     or the embedded operating system.
     94%%     However, the specification of the application will be independent of both the
     95%%     architectural template and the target FPGA device.
     96%%     Basically, the following three architectural templates will be provided:
     97%%     \begin{enumerate}
     98%%     \item A Neutral architectural template based on the SoCLib IP core library and the
     99%%       VCI/OCP communication infrastructure.
     100%%     \item An \altera architectural template based on the \altera IP core library, the
     101%%       AVALON system bus and the NIOS processor.
     102%%     \item A \xilinx architectural template based on the \xilinx IP core library,
     103%%       the \xilinxbus system bus and the \xilinxcpu processor.
     104%%     \end{enumerate}
     105%% \item[Hardware/Software communication middleware:]
     106%%     COACH will implement an homogeneous HW/SW communication infrastructure and
     107%%     communication APIs (Application Programming Interface), that will be used for
     108%%     communications between software tasks running on embedded processors and
     109%%     dedicated hardware coprocessors.
     110%% \item[Interaction with the industrial world:]
     111%%     COACH will not be a closed framework but it will be opened to the industrial
     112%%     world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
     113%%     architectural template and by providing the IP-XACT description of the generated MPSoC.
     114%%     This should facilitate the enhancement of the architectural template with IP and the
     115%%     integration of the IP produced by COACH in larger design.
     116%% \end{description}
     117%% %From the end user point of view, the specification of the application will be
     118%% %independant from both the architectural template and from the selected FPGA
     119%% %family.
     120%% \parlf
     121%% % le programme de travail
     122%% %The COACH project targets fundamental issues related to design methodologies for
     123%% %digital systems by providing estimation, exploration and design tools targeting both
     124%% %performance and power optimization at all the abstraction levels of the flow (system,
     125%% %architecture, algorithm and logic).
     126%% To reach this ambitious goal, the project will rely on the experience and the
     127%% %complementariness
     128%% synergy of the partners in the following domains:
     129%% Operating system and communication middleware (\tima, \upmc),
     130%% MPSoC architectures (\tima, \ubs, \upmc),
     131%% ASIP architectures (\inria),
     132%% High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
     133%% HPC (\bull, \thales, \lip), tools integration in IP-XACT flow (\mds).
     134%% \\
     135%% The COACH project does not start from scratch.
     136%% It relies
     137%% on the Magillem industrial platform for the integration into IP-XACT flows,
     138%% on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
     139%% on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
     140%% on the ROMA~\cite{roma, RAFFIN:2010:INRIA-00539874:1} project for ASIP,
     141%% on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
     142%% transformations,
     143%% and on the \xilinx and \altera IP core libraries.
     144%% Finally it will use the \xilinx and \altera logic and physical synthesis tools
     145%% to generate the FPGA configuration bitstreams.
     146%% %The main development steps of the COACH project are:
     147%% %\begin{enumerate}
     148%% %   \item Definition of the end user inputs:
     149%% %    The coarse grain parallelism of the application will be described as a communicating
     150%% %    task graph, each task being described in C language.
     151%% %    Similarly the architectural templates with their parameters and the design constraints
     152%% %    will be specified.
     153%% %  \item Definition of an internal format for representing task.
     154%% %  \item Development of the GCC pluggin for generating the internal format of a
     155%% %    C task.
     156%% %  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
     157%% %    the internal format. This will allow to swap from one tool to another one, and to
     158%% %    chain them if necessary.
     159%% %  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
     160%% %    platform to generate the bitstream for the various FPGA families and architectural
     161%% %    templates.
     162%% %  \item Development of new tools such as ASIP compiler, HPC design environment and
     163%% %    dynamic reconfiguration of FPGA devices.
     164%% %\end{enumerate}
     165%% \parlf
     166%% The role of the industrial partners \bull, \thales and \mds is to provide
     167%% real use cases to benchmark the COACH design environment and to analyze the designer productivity
     168%% improvements.
     169%% \parlf
     170%% The COACH project will deliver an open and freely distributed infrastructure.
     171%% The architectural templates and most of the software tools will be distributed under the
     172%% GPL-like license.
     173%% The VHDL synthesizable models for the neutral architectural template
     174%% will also be freely available for non commercial use.
     175%% For industrial exploitation the technology providers are ready to propose commercial licenses,
     176%% directly to the end user, or through a third party.
     177%% \parlf
     178%% \mustbecompleted{LIST NON A JOUR}
     179%% The major FPGA companies (\xilinx and \altera) have expressed their interest for
     180%% this project.
     181%% Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the
     182%% "letters of interest" (see Annex B), that have been collected during the preparation of the project :
     183%% ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
     184%% ABOUND Logic, EADS-ASTRIUM.
     185%%

  • anr/section-consortium-people.tex

    r351 r353  
    2222cours.}
    2323
     24\def\doNote#1#2{{\scriptsize-- $^{#1}$#2}}
     25\def\doAbre#1#2{{\mbox{#2$^{#1}$}}\xspace}
     26
    2427\newenvironment{peopletabular}{%
    25   \noindent\begin{tabular}{|p{1.8cm}|p{1.6cm}|p{1.6cm}|p{1.5cm}|p{1.0cm}|p{.6cm}|p{6cm}|}\hline
    26     partner  & Name & F. name & Position & Fields & PM$^{\ast}$ & Contribution to the project \\
    27   }{\end{tabular}\vspace{.75ex}\\
    28     {\hspace*{1cm}\scriptsize $^{\ast}$ total of PM for the 3 years of the project.}}
     28  \let\PMnote\relax    \def\PM{\doAbre{\ast}{PM}\gdef\PMnote{\doNote{\ast}{total of PM for the 3 years of the project.}}}
     29  \let\COnote\relax    \def\CO{\doAbre{a}{coor.}\gdef\COnote{\doNote{a}{coordinator.}}}
     30  \let\REnote\relax    \def\RE{\doAbre{b}{resp.}\gdef\REnote{\doNote{b}{responsible.}}}
     31  \let\MEnote\relax    \def\ME{\doAbre{c}{cont.}\gdef\MEnote{\doNote{c}{contributor.}}}
     32
     33  \let\SPMnote\relax     \def\SPM{\doAbre{A}{S. P. M.}\gdef\SPMnote{\doNote{A}{Strategic Project Manager.}}}
     34  \let\VPENGnote\relax \def\VPENG{\doAbre{B}{VP of eng.}\gdef\VPENGnote{\doNote{B}{VP of Engineering.}}}
     35  \let\RENGnote\relax   \def\RENG{\doAbre{C}{R. engineer}\gdef\RENGnote{\doNote{C}{Research engineer.}}}
     36  \let\INREnote\relax   \def\INRE{\doAbre{D}{I. researcher}\gdef\INREnote{\doNote{D}{Inria researcher.}}}
     37  \let\EPnote\relax       \def\EP{\doAbre{E}{E. professor}\gdef\EPnote{\doNote{E}{Emeritus professor.}}}
     38  \let\APnote\relax       \def\AP{\doAbre{F}{A. professor}\gdef\APnote{\doNote{F}{Assistant professor.}}}
     39  \let\DMnote\relax       \def\DM{\doAbre{G}{D. M.}\gdef\DMnote{\doNote{G}{Department mananger.}}}
     40 %\let\RDENGnote\relax \def\RDENG{\doAbre{H}{R\&D eng.}\gdef\RDENGnote{\doNote{H}{R\&D Engineer.}}}
     41  %
     42  \let\COMPnote\relax   \def\COMP{\doAbre{1}{COMP}\gdef\COMPnote{\doNote{1}{Compilation.}}}
     43  \let\SWnote\relax       \def\SW{\doAbre{2}{SW}\gdef\SWnote{\doNote{2}{SW development.}}}
     44  \let\SYSnote\relax     \def\SYS{\doAbre{3}{SYS}\gdef\SYSnote{\doNote{3}{System design.}}}
     45  \let\VPnote\relax       \def\VP{\doAbre{4}{V.P.}\gdef\VPnote{\doNote{4}{Virtual prototyping.}}}
     46  \let\ARCHnote\relax   \def\ARCH{\doAbre{5}{ARCH}\gdef\ARCHnote{\doNote{5}{Architecture \& micro-architecture.}}}
     47  \let\MMnote\relax       \def\MM{\doAbre{6}{M.M.}\gdef\MMnote{\doNote{6}{Memory management \& FIFO construction \& irregular extensions.}}}
     48  \let\AUPAnote\relax   \def\AUPA{\doAbre{7}{A.P.}\gdef\AUPAnote{\doNote{7}{Process scheduling \& automatic parallelization.}}}
     49  \noindent\hspace{-0.5cm}\begin{minipage}{\linewidth}\small\begin{tabular}{|p{0.7cm}|p{1.4cm}|p{1.7cm}|p{2.3cm}|p{3.9cm}|p{.5cm}|p{5cm}|}\hline
     50    kind  & Name & F. name & Position & Fields & \PM & Contribution to the project \\
     51  }{\end{tabular}\vspace{0.50ex}\\
     52    \PMnote\COnote\REnote\MEnote
     53    \SPMnote\VPENGnote\RENGnote\INREnote\EPnote\APnote\DMnote
     54    \COMPnote\SWnote\SYSnote\VPnote\ARCHnote\MMnote\AUPAnote
     55    --\\\end{minipage}}
     56    %{\hspace*{1cm}\scriptsize $^{\ast}$ total of PM for the 3 years of the project.}}
    2957
    3058\def\peopletabularentry#1{\hline\hline\multicolumn{7}{|l|}{\textsc{#1}}\\\hline}
    … …  
    3361
    3462\peopletabularentry{\mds}           
    35 coordinator & Vaumorin    & Emannuel    & Strategic Project Manager & ESL      & 20 & Project leader \\\hline
    36 contributor & Spasevski   & Cyril       & CTO                 & EDA            & 6 & Technical specifications \\\hline
    37 contributor & Guntz       & St\'ephane  & VP of Engineering   & EDA            & 6 & Demonstrator specification and management \\\hline
    38 contributor & Lucas       & Ronan       & R\&D Engineer       & HW/SW Codesign & 9 & Tools and demonstrator implementation \\\hline
    39 contributor & Olivier     & Garry       & R\&D Engineer       & SW development & 9 & Tools and demonstrator implementation \\\hline
    40 
     63\CO & Vaumorin    & Emannuel    & \SPM                & ESL            & 20& Task: 1 (\RE), \mustbecompleted{X, Y}, 8 (\RE)\\\hline
     64\ME & Spasevski   & Cyril       & CTO                 & EDA            & 6 & Task: \mustbecompleted{X, Y} \\\hline
     65\ME & Guntz       & St\'ephane  & \VPENG              & EDA            & 6 & Task: \mustbecompleted{X, Y} \\\hline
     66\ME & Lucas       & Ronan       & R\&D Engineer       & Codesign       & 9 & Task: \mustbecompleted{X, Y} \\\hline
     67\ME & Olivier     & Garry       & R\&D Engineer       & SW dev.        & 9 & Task: \mustbecompleted{X, Y} \\\hline
     68%\end{peopletabular}\begin{peopletabular}
    4169\peopletabularentry{\inria}
    42 responsible        & Charot      & François      & INRIA researcher&SOC ASIP         & 12 & expertise in architecture, microarchitecture, SoC design. Participation to Task-1/2/4/8  \\\hline
    43 contributor         & Derrien      & Steven      & Associate professor&
    44 HLS compilation          & 6& expertise in architecture, microarchitecture, SoC design \\\hline
    45 
     70\RE & Charot      & François     & \mbox{\INRE}       & SOC ASIP \ARCH     & 12 & Task: 1, 2, 4, 8 \\\hline
     71\ME & Derrien      & Steven      & \mbox{\AP}         & HLS \COMP  \ARCH   &  6 & Task: \mustbecompleted{X, Y} \\\hline
     72%\end{peopletabular}\begin{peopletabular}
    4673\peopletabularentry{\lip}
    47 responsible & Alias       & Christophe  & Researcher (CR2) at Inria  & Compilers, HPC & 15 & Memory management and FIFO construction. Irregular extensions.\\\hline
    48 contributor & Feautrier   & Paul        & emeritus professor  & Compilers     & 13 & Process scheduling and building.
    49                                                                                     Automatic Parallelization \\ \hline
    50 
     74\RE & Alias       & Christophe  & \mbox{\INRE}        & \COMP HPC \MM    & 15 & Task: 1, 2, 4 (\RE), 8 \mustbecompleted{X, Y} \\\hline
     75\ME & Feautrier   & Paul        & \mbox{\EP}          & \COMP \AUPA      & 13 & Task: \mustbecompleted{X, Y} \\\hline
     76%\end{peopletabular}\begin{peopletabular}
    5177\peopletabularentry{\tima}
    52 responsible & P\'etrot    & Fr\'ed\'eric& professor           & SOC HLS HPC & 12  & Architecture and micro-architecture, OS design, virtual prototyping, HLS. Participation to Task-1/2/3/5/6\\\hline
    53             & Muller      & Olivier     & Associate professor & SOC HLS     & 16  & SOC design and prototyping on FPGA \\\hline
    54             & Prost-Boucle& Adrien      & PhD candidate       & SOC HLS     & 24  & FPGA Configuration\\\hline
    55 ...         & ...         & ...         & ...                 & ...         & ... & ... \\\hline
    56 
     78\RE & P\'etrot    & Fr\'ed\'eric& professor           & SOC HLS HPC OS \VP \ARCH & 12 & Task: 1, 2, 3, 5, 6 \\\hline
     79\ME & Muller      & Olivier     & \mbox{\AP}          & SOC \VP HLS              & 16 & Task: \mustbecompleted{X, Y} \\\hline
     80\ME & Prost-Boucle& Adrien      & PhD candidate       & SOC HLS                  & 24 & Task: \mustbecompleted{X, Y} \\\hline
     81%\end{peopletabular}\begin{peopletabular}
    5782\peopletabularentry{\ubs}
    58 responsible & Coussy      & Philippe    & Associate Professor & SOC HLS         & 12 & Architecture, microarchitecture, HLS, virtual prototyping, SoC ign \\\hline
    59 contributor & Heller      & Dominique   & Research engineer   & Compilers HLS & 8 & Architecture, microarchitecture, compilation, HLS\\\hline
    60 contributor & Chavet      & Cyrille     & Associate Professor & SOC HLS         & 4 & Architecture,
    61  HLS \\\hline
     83\RE & Coussy      & Philippe    & \mbox{\AP}           & SOC HLS \ARCH \VP        & 12 & Task: 1, 2, 5 (\RE), \mustbecompleted{X, Y}, 8 \\\hline
     84\ME & Heller      & Dominique   & \mbox{\RENG}         & \COMP HLS \ARCH          &  8 & Task: \mustbecompleted{X, Y} \\\hline
     85\ME & Chavet      & Cyrille     & \mbox{\AP}           & SOC HLS \ARCH            &  4 & Task: \mustbecompleted{X, Y} \\\hline
     86%\end{peopletabular}\begin{peopletabular}
     87\peopletabularentry{\upmc}
     88\RE & Greiner     & Alain       & professor           & SOC \ARCH \VP            & 12 & Task: 1, 2 (\RE), 3, 6 \\\hline
     89\ME & Aug\'{e}    & Ivan        & \AP                 & HLS \SW SOC HPC          & 16 & Task: 1, 3, 3 (\RE), 5, 6, 8 \\\hline
     90%\end{peopletabular}\begin{peopletabular}
     91\peopletabularentry{\bull}           
     92\RE & Nguyen      & Huy-Nam     & \DM                 & HPC \SYS \VP CAD   &  9 & Task: 1, 2, 6 (\RE), 7, 8 \\\hline
     93\end{peopletabular}\begin{peopletabular}
     94\peopletabularentry{\thales}                       
     95\RE & Lemonier    & Fabrice     & ...                 & ...                & ... & Task: \mustbecompleted{X, Y} 7 (\RE) \\\hline
    6296\end{peopletabular}
    63 
    64 \begin{peopletabular}
    65 \peopletabularentry{\upmc}
    66 responsible & Greiner     & Alain       & professor           & SOC         & 12  & Expertise in MPSoC design, virtual prototyping, micro-architecture.
    67                                                                                     Responsible of Task-2. Participation to Task-3/6. \\\hline
    68 member      & Aug\'{e}    & Ivan        & assistant professor & HLS SOC HPC & 16  & Expertise in HLS, software development, kernel, SoC design, micro-architecture.
    69                                                                                     Responsible of Task-3. Participation to Task-2/5/6/8. \\\hline
    70                                        
    71 \peopletabularentry{\bull}           
    72 responsible & Nguyen      & Huy-Nam     & Dept. mananger      & HPC CAD     & 9
    73 & Experiences in HPC, System Design and Prototyping, Responsible of Task-6. \\\hline
    74                                                      
    75 \peopletabularentry{\thales}                       
    76 responsible & Lemonier    & Fabrice     & ...                 & ...         & ... & ... \\\hline
    77 ...         & ...         & ...         & ...                 & ...         & ... & ... \\\hline
    78 \end{peopletabular}

  • anr/section-project-description.tex

    r346 r353  
    1010
    1111
    12 \begin{figure}\leavevmode\center
    13 \includegraphics[width=.8\linewidth]{architecture-csg}
     12\begin{figure}[h!]\leavevmode\center
     13\includegraphics[width=.7\linewidth]{architecture-csg}
    1414\caption{\label{archi-csg} Software architecture for digital system generation}
    1515%\end{figure}\begin{figure}\leavevmode\center
    16 \mbox{}\vspace*{1ex}\\
     16%\mbox{}\vspace*{1ex}\\
    1717\includegraphics[width=1.0\linewidth]{architecture-hls}
    1818\caption{\label{archi-hls} Software architecture of hardware accellerator synthesis}
    1919%\end{figure}\begin{figure}\leavevmode\center
    20 \mbox{}\vspace*{1ex}\\
    21 \includegraphics[width=.8\linewidth]{architecture-hpc}
     20%\mbox{}\vspace*{1ex}\\
     21\includegraphics[width=.65\linewidth]{architecture-hpc}
    2222\caption{\label{archi-hpc} Performance analysis of a HPC partitionning}
    2323\end{figure}
    … …  
    120120\begin{figure}\leavevmode\center
    121121%\includegraphics[width=.4\linewidth]{dependence-task}
    122 \includegraphics[width=0.70\linewidth]{dependence-task-h}
     122\includegraphics[width=0.50\linewidth]{dependence-task-h}
    123123\caption{\label{dependence-task}Task dependencies}
    124124\end{figure}

  • anr/section-project-task-schedule.tex

    r348 r353  
    136136\parlf
    137137Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}.
    138 \begin{figure}\leavevmode\center
     138\begin{figure}[t]\leavevmode\center
    139139{
    140140\fontsize{7pt}{9pt}\selectfont

  • anr/section-ressources.tex

    r351 r353  
    5050  The table below summarizes the manpower in \hommemois by tasks for both permanent and
    5151  non-permanent personnels. The detail by deliverables is given in
    52   figure~\ref{table-livrables-1}.
     52  annexe~\ref{table-livrables-inria} (page \pageref{table-livrables-inria}).
    5353  The non-permanent personnels costs represent {48\%} of the personnal
    5454  costs. The requested funding for non permanent personnels is 100\% of
    … …  
    8181  practical skills, that will be able to get a sufficient
    8282  understanding of the polyhedral techniques to produce a working
    83   implementation.  \parlf The table below summarizes the \hommemois by
    84   deliverables and tasks for both permanent and non-permanent
    85   personnels.  The effort of permanent personnels represents 61\% of
     83  implementation.
     84  \parlf
     85  The table below summarizes the \hommemois by tasks for both permanent
     86  and non-permanent personnels.
     87  Annexe~\ref{table-livrables-lip} (page \pageref{table-livrables-lip})
     88  details this table at the deliverable level.
     89  The effort of permanent personnels represents 61\% of
    8690  the total effort. The non-permanent personnels costs represents
    87   52\% of the personnal costs. The requested funding for non permanent
     91  52\% of the personal costs. The requested funding for non permanent
    8892  personnels is 100\% of the total ANR requested
    89   funding.  \begin{center}\input{table_inria_compsys_full.tex}\end{center}
     93  funding.
     94  \begin{center}\input{table_inria_compsys_short.tex}\end{center}
    9095\item [Subcontracting]
    9196  No subcontracting costs.
    … …  
    121126  The table below summarizes the man power in \hommemois by tasks for both permanent and
    122127  non-permanent personnels. The detail by deliverables is given in
    123   figure~\ref{table-livrables-1}.
     128  annexe~\ref{table-livrables-tima} (page \pageref{table-livrables-tima}).
    124129  The effort of permanent personnels represents 50\% of the total effort.
    125130  The requested funding for non permanent personnels is 86\% of the total ANR requested
    … …  
    151156  \parlf
    152157  The table below sumarizes the man power in \hommemois by tasks for both permanent and
    153   non-permanent personnels. The detail by deliverables is given in
    154   figure~\ref{table-livrables-2}.
     158  non-permanent personnels. The detail by deliverables is given in 
     159  annexe~\ref{table-livrables-usb} (page \pageref{table-livrables-usb}).
    155160  The non-permanent personnels costs represent 50\% of the personnal costs.
    156161  The requested funding for non permanent personnels is about 83\% of the total ANR
    … …  
    183188    The table below sumarizes the man power by tasks in \hommemois for both permanent  and
    184189    non-permanent personnels.
    185     The detail by deliverables is given in figure~\ref{table-livrables-2}.
     190    The detail by deliverables is given in annexe~\ref{table-livrables-upmc} (page \pageref{table-livrables-upmc}).
    186191    The non-permanent personnels costs (24 \hommemois) represent 46\% of the personnal costs.
    187192    The requested funding for non permanent personnels is 79\% of the total ANR
    … …  
    208213  \mds employees involved in the project are permanent managers, engineers and PhD graduates.
    209214  The man power detail in \hommemois by deliverables is given in
    210   figure~\ref{table-livrables-1} and a sumary by task in the following table.
     215  annexe~\ref{table-livrables-mds} (page \pageref{table-livrables-mds}).
     216  and a sumary by task in the following table.
    211217  \begin{center}\input{table_mds_short.tex}\end{center}
    212218\item[Subcontracting]
    … …  
    227233    Bull in COACH. It is estimated at about 5\% (tbc) of the total funding.
    228234\item[Personnel costs]
    229     A permanent engineer will be assigned full time to the project for a duration of 20
    230     months as shown in the table below that gives the man power in \hommemois:
    231     \begin{center}\input{table_bull_full.tex}\end{center}
     235    A permanent engineer will be assigned full time to the project for a duration of 36
     236    months as shown in the table below that summarizes the man power in \hommemois.
     237    The detail  by deliverables is given in
     238    annexe~\ref{table-livrables-bull} (page \pageref{table-livrables-bull}).
     239    \begin{center}\input{table_bull_short.tex}\end{center}
    232240\item[Subcontracting]
    233241    No subcontracting costs.
    … …  
    251259    estimated to 13 \hommemois.
    252260    The effort to describe and develop the application is estimated to 14 \hommemois.
    253     Finally we need one man*month for the partiticipation to the global specification in task 2.
    254     This is sumarized in the table below:
    255     \begin{center}\input{table_thales_full.tex}\end{center}
     261    Finally we need one man*month for the participation to the global specification in task 2.
     262    This is summarized in the table below and detailed by deliverables in
     263    annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales}).
     264    \begin{center}\input{table_thales_short.tex}\end{center}
    256265\item[Subcontracting]
    257266    No subcontracting costs.
    … …  
    266275%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    267276%
    268 \begin{landscape}
    269 \begin{figure}
    270 \begin{small}
    271 \settowidth\desclen{XILINX RTL optimisation (5)}
    272 \def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
    273 \begin{minipage}[b]{.47\linewidth}\center
    274 \input{table_inria_cairn_full.tex}\vspace{.5ex}\\  \inria  \vspace{2.5ex}\\
    275 \input{table_mds_full.tex}\vspace{.5ex}\\       \mds \\
    276 \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center
    277 \input{table_tima_full.tex}\vspace{.5ex} \\ \tima
    278 \end{minipage}
    279 \end{small}
    280 \caption{\label{table-livrables-1} Man power in \hommemois for the deliverables (1)}
    281 \end{figure}
    282 %
    283 \begin{figure}
    284 \begin{small}
    285 \settowidth\desclen{XILINX RTL optimisation (5)}
    286 \def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
    287 \begin{minipage}[b]{.47\linewidth}\center
    288 \input{table_ubs_full.tex}\vspace{.5ex}\\     \ubs    \vspace{2.5ex}\\
    289 %\input{table_thales_full.tex}\vspace{.5ex}\\  \thales \\
    290 \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center
    291 \input{table_upmc_full.tex}\vspace{.5ex} \\   \upmc
    292 \end{minipage}
    293 \end{small}
    294 \caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (2)}
    295 \end{figure}
    296 \end{landscape}
    297 %
    298 %\begin{landscape}
    299 %\begin{figure}
    300 %\begin{small}
    301 %\settowidth\desclen{XILINX RTL optimisation (5)}
    302 %\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
    303 %\hfill
    304 %\begin{minipage}[b]{.47\linewidth}\center
    305 %\input{table_inria_compsys_full.tex}\vspace{.5ex}\\     \lip    \vspace{2.5ex}\\
    306 %\end{minipage}\hfill
    307 %\end{small}
    308 %\caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (3)}
    309 %\end{figure}
    310 %\end{landscape}
     277% \begin{landscape}
     278% \begin{figure}
     279% \begin{small}
     280% \settowidth\desclen{XILINX RTL optimisation (5)}
     281% \def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
     282% \begin{minipage}[b]{.47\linewidth}\center
     283% \input{table_inria_cairn_full.tex}\vspace{.5ex}\\  \inria  \vspace{2.5ex}\\
     284% \input{table_mds_full.tex}\vspace{.5ex}\\       \mds \\
     285% \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center
     286% \input{table_tima_full.tex}\vspace{.5ex} \\ \tima
     287% \end{minipage}
     288% \end{small}
     289% \caption{\label{table-livrables-1} Man power in \hommemois for the deliverables (1)}
     290% \end{figure}
     291% %
     292% \begin{figure}
     293% \begin{small}
     294% \settowidth\desclen{XILINX RTL optimisation (5)}
     295% \def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
     296% \begin{minipage}[b]{.47\linewidth}\center
     297% \input{table_ubs_full.tex}\vspace{.5ex}\\     \ubs    \vspace{2.5ex}\\
     298% %\input{table_thales_full.tex}\vspace{.5ex}\\  \thales \\
     299% \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center
     300% \input{table_upmc_full.tex}\vspace{.5ex} \\   \upmc
     301% \end{minipage}
     302% \end{small}
     303% \caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (2)}
     304% \end{figure}
     305% \end{landscape}
     306% %
     307% %\begin{landscape}
     308% %\begin{figure}
     309% %\begin{small}
     310% %\settowidth\desclen{XILINX RTL optimisation (5)}
     311% %\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
     312% %\hfill
     313% %\begin{minipage}[b]{.47\linewidth}\center
     314% %\input{table_inria_compsys_full.tex}\vspace{.5ex}\\     \lip    \vspace{2.5ex}\\
     315% %\end{minipage}\hfill
     316% %\end{small}
     317% %\caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (3)}
     318% %\end{figure}
     319% %\end{landscape}
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