Index: anr/section-1.tex
===================================================================
--- anr/section-1.tex	(revision 337)
+++ anr/section-1.tex	(revision 353)
@@ -1,159 +1,14 @@
-% les objectifs globaux, 
-The market of digital systems is about 4,600 M\$ today and is estimated to
-5,600 M\$ in 2012. However the ever growing application complexity involves
-integration of heterogeneous technologies and requires the design of
-complex Multi-Processors System on Chip (MPSoC).
-\\
-During the last decade, the use of ASICs (Application Specific
-Integrated Circuits) appeared to be more and more reserved to high volume markets, because
-the design and fabrication costs of such components exploded, due to increasing NRE (Non
-Recurring-Engineering) costs.
-Fortunately, FPGA (Field Programmable Gate Array) components, such as the
-Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
-implement a complete MPSoC with multiple processors and several dedicated
-coprocessors for a few Keuros per device.
-\\
-Many applications are initially captured 
-algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest 
-in tools that can provide an implementation path directly from HLLs to hardware. 
-Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
-Co-design, High-Level Synthesis...) are now mature and allow the automation of
-a system-level design flow. Unfortunately, ESL tool development to date has primarily focused 
-on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). 
-However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design 
-methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting 
-designs written in the C/C++ language and implementing the function directly into FPGA. 
-We believe that coupling FPGA technologies and ESL methodologies
-will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
-devices and to enter new, low and medium volume markets.
-Furthermore, today there is an increasing industrial interest into IC
-that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
-such as the ATOM E600C chip (Intel).
-In few a years, one can expect that such chips will become current. Even standard
-general purpose CPU cores will contains a configurable area
-bringing an explosion in low and medium volume markets.
+The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs (Application Specific Integrated Circuits) appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
 \parlf
-The objective of COACH is to provide an integrated design flow for the design of
-multi-processors digital systems targeting FPGA devices.
-It will be dedicated to system/software designers, and hide as much as possible
-the hardware characteristics to the end-user.
-COACH will mainly target three kinds of digital systems: 
-1) embedded and autonomous application such as  personal digital assistants (PDA),
-   ambient computing components, or wireless sensor networks (WSN);
-2) PCI/E extension boards connected to a PC to accelerate a specific application,
-   it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
-3) sub-system application for generating an IP to a larger system.
-\parlf
-%verrous scientifiques et techniques
-The COACH environment will integrate several hardware and software technologies:
-\begin{description}
-\item[Design Space Exploration:]
-    The COACH environment will allow to describe an application as a process 
-	network i.e. a set of tasks communicating through FIFO channels.
-	COACH will allow to map the application on a shared-memory, MPSoC architecture. 
-    It will permit to easily explore the design space to help the system designer 
-	to define the proper hardware/software partitioning of the application.
-    For each point in the design space, metrics such as throughput, latency, power
-    consumption, silicon area, memory allocation and data locality will be provided.
-\item[Hardware Accelerators Synthesis (HAS):]
-    COACH will allow the automatic generation of hardware accelerators when required.
-    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
-    (ASIP) design environments and source-level transformation tools (loop transformations
-    and memory optimization) will be provided.
-    This will allow further exploration of the micro-architectural design space.
-    HLS tools are sensitive to the coding style of the input specification and the domain
-    they target (control vs. data dominated).
-    The HLS tools of COACH will support a common language and coding style to avoid
-    re-engineering by the designer.
-\item[Platform based design:] 
-    COACH will handle both \altera and \xilinx FPGA devices.
-    COACH will define architectural templates that can be customized by adding
-    dedicated coprocessors and ASIPs and by fixing template parameters such as
-    the number of embedded processors, the number and size of embedded memory banks
-    or the embedded operating system.
-    However, the specification of the application will be independent of both the
-    architectural template and the target FPGA device.
-    Basically, the following three architectural templates will be provided:
-    \begin{enumerate}
-    \item A Neutral architectural template based on the SoCLib IP core library and the
-      VCI/OCP communication infrastructure.
-    \item An \altera architectural template based on the \altera IP core library, the
-      AVALON system bus and the NIOS processor.
-    \item A \xilinx architectural template based on the \xilinx IP core library,
-      the \xilinxbus system bus and the \xilinxcpu processor.
-    \end{enumerate}
-\item[Hardware/Software communication middleware:]
-    COACH will implement an homogeneous HW/SW communication infrastructure and
-    communication APIs (Application Programming Interface), that will be used for 
-    communications between software tasks running on embedded processors and 
-    dedicated hardware coprocessors.
-\item[Interaction with the industrial world:]
-    COACH will not be a closed framework but it will be opened to the industrial
-    world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
-    architectural template and by providing the IP-XACT description of the generated MPSoC.
-    This should facilitate the enhancement of the architectural template with IP and the
-    integration of the IP produced by COACH in larger design.
-\end{description}
-%From the end user point of view, the specification of the application will be
-%independant from both the architectural template and from the selected FPGA
-%family.
-\parlf
-% le programme de travail
-%The COACH project targets fundamental issues related to design methodologies for 
-%digital systems by providing estimation, exploration and design tools targeting both 
-%performance and power optimization at all the abstraction levels of the flow (system, 
-%architecture, algorithm and logic).
-To reach this ambitious goal, the project will rely on the experience and the
-%complementariness
-synergy of the partners in the following domains:
-Operating system and communication middleware (\tima, \upmc),
-MPSoC architectures (\tima, \ubs, \upmc),
-ASIP architectures (\inria),
-High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
-HPC (\bull, \thales, \lip), tools integration in IP-XACT flow (\mds).
-\\
-The COACH project does not start from scratch.
-It relies
-on the Magillem industrial platform for the integration into IP-XACT flows,
-on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
-on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
-on the ROMA~\cite{roma, RAFFIN:2010:INRIA-00539874:1} project for ASIP,
-on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
-transformations,
-and on the \xilinx and \altera IP core libraries.
-Finally it will use the \xilinx and \altera logic and physical synthesis tools
-to generate the FPGA configuration bitstreams.
-%The main development steps of the COACH project are: 
-%\begin{enumerate}
-%   \item Definition of the end user inputs:
-%    The coarse grain parallelism of the application will be described as a communicating
-%    task graph, each task being described in C language.
-%    Similarly the architectural templates with their parameters and the design constraints
-%    will be specified.
-%  \item Definition of an internal format for representing task.
-%  \item Development of the GCC pluggin for generating the internal format of a
-%    C task.
-%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
-%    the internal format. This will allow to swap from one tool to another one, and to
-%    chain them if necessary.
-%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
-%    platform to generate the bitstream for the various FPGA families and architectural
-%    templates.
-%  \item Development of new tools such as ASIP compiler, HPC design environment and
-%    dynamic reconfiguration of FPGA devices.
-%\end{enumerate}
-\parlf
-The role of the industrial partners \bull, \thales and \mds is to provide
-real use cases to benchmark the COACH design environment and to analyze the designer productivity 
-improvements. 
-\parlf
-The COACH project will deliver an open and freely distributed infrastructure.
-The architectural templates and most of the software tools will be distributed under the
-GPL-like license.
-The VHDL synthesizable models for the neutral architectural template
-will also be freely available for non commercial use.
-For industrial exploitation the technology providers are ready to propose commercial licenses,
-directly to the end user, or through a third party.
-\parlf
+Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow. Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both Small and Medium Enterprise and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest to IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. Probably in few years, such chips will become current and even standard general purpose CPU cores will contains a configurable area making explode the low and medium volume markets of digital systems. COACHâs objective is to provide an integrated design flow for the design of multi-processors digital systems targeting FPGA devices. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application such as personal digital assistants (PDA), ambient computing components, or wireless sensor networks, 2/ PCI-E extension boards connected to a PC to accelerate a specific application, it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing, 3/ Sub-system application for generating an IP to a larger system. The COACH open-source environment will integrate several hardware and software technologies:
+%
+\begin{itemize}
+\item Design Space Exploration by allowing to describe an application as a process network i.e. a set of tasks communicating through FIFO channels and to map the application on a shared-memory, MPSoC architecture.
+\item Hardware Accelerators Synthesis by allowing the automatic generation of hardware accelerators when required
+\item Platform based design: three architectural templates will be provided (free-generic and ALTERA and XILINXâs IPs based).
+\item Hardware/Software communication middleware by implementing an homogeneous HW/SW communication infrastructure and communication APIs (Application Programming Interface), that will be used for communications between software tasks running on embedded processors and dedicated hardware coprocessors.
+\item Interaction with the industrial world: the framework will be open to the industrial world by using IP-XACT standard for describing the components of the architectural template and by providing the IP-XACT description of the generated MPSoC.
+\end{itemize}
+%
 \mustbecompleted{LIST NON A JOUR}
 The major FPGA companies (\xilinx and \altera) have expressed their interest for
@@ -164,2 +19,167 @@
 ABOUND Logic, EADS-ASTRIUM.
 
+%% % les objectifs globaux, 
+%% The market of digital systems is about 4,600 M\$ today and is estimated to
+%% 5,600 M\$ in 2012. However the ever growing application complexity involves
+%% integration of heterogeneous technologies and requires the design of
+%% complex Multi-Processors System on Chip (MPSoC).
+%% \\
+%% During the last decade, the use of ASICs (Application Specific
+%% Integrated Circuits) appeared to be more and more reserved to high volume markets, because
+%% the design and fabrication costs of such components exploded, due to increasing NRE (Non
+%% Recurring-Engineering) costs.
+%% Fortunately, FPGA (Field Programmable Gate Array) components, such as the
+%% Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
+%% implement a complete MPSoC with multiple processors and several dedicated
+%% coprocessors for a few Keuros per device.
+%% \\
+%% Many applications are initially captured 
+%% algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest 
+%% in tools that can provide an implementation path directly from HLLs to hardware. 
+%% Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
+%% Co-design, High-Level Synthesis...) are now mature and allow the automation of
+%% a system-level design flow. Unfortunately, ESL tool development to date has primarily focused 
+%% on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). 
+%% However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design 
+%% methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting 
+%% designs written in the C/C++ language and implementing the function directly into FPGA. 
+%% We believe that coupling FPGA technologies and ESL methodologies
+%% will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
+%% devices and to enter new, low and medium volume markets.
+%% Furthermore, today there is an increasing industrial interest into IC
+%% that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
+%% such as the ATOM E600C chip (Intel).
+%% In few a years, one can expect that such chips will become current. Even standard
+%% general purpose CPU cores will contains a configurable area
+%% bringing an explosion in low and medium volume markets.
+%% \parlf
+%% The objective of COACH is to provide an integrated design flow for the design of
+%% multi-processors digital systems targeting FPGA devices.
+%% It will be dedicated to system/software designers, and hide as much as possible
+%% the hardware characteristics to the end-user.
+%% COACH will mainly target three kinds of digital systems: 
+%% 1) embedded and autonomous application such as  personal digital assistants (PDA),
+%%    ambient computing components, or wireless sensor networks (WSN);
+%% 2) PCI/E extension boards connected to a PC to accelerate a specific application,
+%%    it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
+%% 3) sub-system application for generating an IP to a larger system.
+%% \parlf
+%% %verrous scientifiques et techniques
+%% The COACH environment will integrate several hardware and software technologies:
+%% \begin{description}
+%% \item[Design Space Exploration:]
+%%     The COACH environment will allow to describe an application as a process 
+%% 	network i.e. a set of tasks communicating through FIFO channels.
+%% 	COACH will allow to map the application on a shared-memory, MPSoC architecture. 
+%%     It will permit to easily explore the design space to help the system designer 
+%% 	to define the proper hardware/software partitioning of the application.
+%%     For each point in the design space, metrics such as throughput, latency, power
+%%     consumption, silicon area, memory allocation and data locality will be provided.
+%% \item[Hardware Accelerators Synthesis (HAS):]
+%%     COACH will allow the automatic generation of hardware accelerators when required.
+%%     Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
+%%     (ASIP) design environments and source-level transformation tools (loop transformations
+%%     and memory optimization) will be provided.
+%%     This will allow further exploration of the micro-architectural design space.
+%%     HLS tools are sensitive to the coding style of the input specification and the domain
+%%     they target (control vs. data dominated).
+%%     The HLS tools of COACH will support a common language and coding style to avoid
+%%     re-engineering by the designer.
+%% \item[Platform based design:] 
+%%     COACH will handle both \altera and \xilinx FPGA devices.
+%%     COACH will define architectural templates that can be customized by adding
+%%     dedicated coprocessors and ASIPs and by fixing template parameters such as
+%%     the number of embedded processors, the number and size of embedded memory banks
+%%     or the embedded operating system.
+%%     However, the specification of the application will be independent of both the
+%%     architectural template and the target FPGA device.
+%%     Basically, the following three architectural templates will be provided:
+%%     \begin{enumerate}
+%%     \item A Neutral architectural template based on the SoCLib IP core library and the
+%%       VCI/OCP communication infrastructure.
+%%     \item An \altera architectural template based on the \altera IP core library, the
+%%       AVALON system bus and the NIOS processor.
+%%     \item A \xilinx architectural template based on the \xilinx IP core library,
+%%       the \xilinxbus system bus and the \xilinxcpu processor.
+%%     \end{enumerate}
+%% \item[Hardware/Software communication middleware:]
+%%     COACH will implement an homogeneous HW/SW communication infrastructure and
+%%     communication APIs (Application Programming Interface), that will be used for 
+%%     communications between software tasks running on embedded processors and 
+%%     dedicated hardware coprocessors.
+%% \item[Interaction with the industrial world:]
+%%     COACH will not be a closed framework but it will be opened to the industrial
+%%     world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
+%%     architectural template and by providing the IP-XACT description of the generated MPSoC.
+%%     This should facilitate the enhancement of the architectural template with IP and the
+%%     integration of the IP produced by COACH in larger design.
+%% \end{description}
+%% %From the end user point of view, the specification of the application will be
+%% %independant from both the architectural template and from the selected FPGA
+%% %family.
+%% \parlf
+%% % le programme de travail
+%% %The COACH project targets fundamental issues related to design methodologies for 
+%% %digital systems by providing estimation, exploration and design tools targeting both 
+%% %performance and power optimization at all the abstraction levels of the flow (system, 
+%% %architecture, algorithm and logic).
+%% To reach this ambitious goal, the project will rely on the experience and the
+%% %complementariness
+%% synergy of the partners in the following domains:
+%% Operating system and communication middleware (\tima, \upmc),
+%% MPSoC architectures (\tima, \ubs, \upmc),
+%% ASIP architectures (\inria),
+%% High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
+%% HPC (\bull, \thales, \lip), tools integration in IP-XACT flow (\mds).
+%% \\
+%% The COACH project does not start from scratch.
+%% It relies
+%% on the Magillem industrial platform for the integration into IP-XACT flows,
+%% on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
+%% on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
+%% on the ROMA~\cite{roma, RAFFIN:2010:INRIA-00539874:1} project for ASIP,
+%% on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
+%% transformations,
+%% and on the \xilinx and \altera IP core libraries.
+%% Finally it will use the \xilinx and \altera logic and physical synthesis tools
+%% to generate the FPGA configuration bitstreams.
+%% %The main development steps of the COACH project are: 
+%% %\begin{enumerate}
+%% %   \item Definition of the end user inputs:
+%% %    The coarse grain parallelism of the application will be described as a communicating
+%% %    task graph, each task being described in C language.
+%% %    Similarly the architectural templates with their parameters and the design constraints
+%% %    will be specified.
+%% %  \item Definition of an internal format for representing task.
+%% %  \item Development of the GCC pluggin for generating the internal format of a
+%% %    C task.
+%% %  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
+%% %    the internal format. This will allow to swap from one tool to another one, and to
+%% %    chain them if necessary.
+%% %  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
+%% %    platform to generate the bitstream for the various FPGA families and architectural
+%% %    templates.
+%% %  \item Development of new tools such as ASIP compiler, HPC design environment and
+%% %    dynamic reconfiguration of FPGA devices.
+%% %\end{enumerate}
+%% \parlf
+%% The role of the industrial partners \bull, \thales and \mds is to provide
+%% real use cases to benchmark the COACH design environment and to analyze the designer productivity 
+%% improvements. 
+%% \parlf
+%% The COACH project will deliver an open and freely distributed infrastructure.
+%% The architectural templates and most of the software tools will be distributed under the
+%% GPL-like license.
+%% The VHDL synthesizable models for the neutral architectural template
+%% will also be freely available for non commercial use.
+%% For industrial exploitation the technology providers are ready to propose commercial licenses,
+%% directly to the end user, or through a third party.
+%% \parlf
+%% \mustbecompleted{LIST NON A JOUR}
+%% The major FPGA companies (\xilinx and \altera) have expressed their interest for
+%% this project.
+%% Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the 
+%% "letters of interest" (see Annex B), that have been collected during the preparation of the project :
+%% ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
+%% ABOUND Logic, EADS-ASTRIUM.
+%% 
