Index: anr/section-1.tex
===================================================================
--- anr/section-1.tex	(revision 353)
+++ anr/section-1.tex	(revision 357)
@@ -1,3 +1,3 @@
-The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs (Application Specific Integrated Circuits) appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
+The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs (Application Specific Integrated Circuits) appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, FPGA (Field Programmable Gate Array) components, such as the Virtex6 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
 \parlf
 Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow. Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both Small and Medium Enterprise and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest to IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. Probably in few years, such chips will become current and even standard general purpose CPU cores will contains a configurable area making explode the low and medium volume markets of digital systems. COACHâs objective is to provide an integrated design flow for the design of multi-processors digital systems targeting FPGA devices. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application such as personal digital assistants (PDA), ambient computing components, or wireless sensor networks, 2/ PCI-E extension boards connected to a PC to accelerate a specific application, it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing, 3/ Sub-system application for generating an IP to a larger system. The COACH open-source environment will integrate several hardware and software technologies:
@@ -30,5 +30,5 @@
 %% Recurring-Engineering) costs.
 %% Fortunately, FPGA (Field Programmable Gate Array) components, such as the
-%% Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
+%% Virtex6 family from \xilinx or the Stratix4 family from \altera, can nowadays
 %% implement a complete MPSoC with multiple processors and several dedicated
 %% coprocessors for a few Keuros per device.
