Index: /anr/anr.sty =================================================================== --- /anr/anr.sty (revision 34) +++ /anr/anr.sty (revision 35) @@ -4,4 +4,7 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newwrite\ganttdata +\immediate\openout\ganttdata=anr.gantt + \def\enable{enable} \def\disable{disable} @@ -60,13 +63,17 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcount\taskcnt\taskcnt=-1 +\newcount\subtaskcnt +\newcount\livrablecnt \newenvironment{workpackage}[1]% -{\newcount\wpcnt\wpcnt=0% - \def\taskname{#1}% +{\global\advance\taskcnt1 + \global\subtaskcnt0 + \def\taskname{T\the\taskcnt}% \begin{description}% \let\itemsave\item% \def\item{% - \advance\wpcnt1 - \def\wpname{\taskname-\the\wpcnt}% - \itemsave[\wpname]}} + \global\advance\subtaskcnt1 + \def\subtaskname{S\taskname-\the\subtaskcnt}% + \itemsave[\subtaskname]}} {\end{description}} @@ -74,7 +81,28 @@ \newenvironment{livrable}% {% + \livrablecnt-1 \ifvmode\else\\\fi \def\item##1##2##3##4##5##6{% - \gdef\name{\wpname##1}% + \def\tmpa{##1}\def\vers{} + \def\tmp{} \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{VF}\fi% + \def\tmp{1} \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\fi% + \def\tmp{V1}\ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\fi% + \def\tmp{2} \ifx\tmp\tmpa\def\vers{V2}\fi% + \def\tmp{V2}\ifx\tmp\tmpa\def\vers{V2}\fi% + \def\tmp{3} \ifx\tmp\tmpa\def\vers{V3}\fi% + \def\tmp{V3}\ifx\tmp\tmpa\def\vers{V3}\fi% + \def\tmp{F} \ifx\tmp\tmpa\def\vers{VF}\fi% + \def\tmp{VF}\ifx\tmp\tmpa\def\vers{VF}\fi% + %\gdef\name{D-\the\taskcnt\the\subtaskcnt\the\livrablecnt-##1}% + \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% + { + \let\xcoach\relax + \let\xilinx\relax + \let\altera\relax + \immediate\write\ganttdata{% + T=\the\taskcnt\space S=\the\subtaskcnt\space% + DV=\the\livrablecnt\space BM=##2 EM=##3 TITLE=##6% + } + } \\\hline \begin{small}\textsc{\name}\end{small} & Index: /anr/task-0.tex =================================================================== --- /anr/task-0.tex (revision 34) +++ /anr/task-0.tex (revision 35) @@ -23,16 +23,16 @@ patners to sign it. \begin{livrable} - \item{-VF}{0}{6}{d}{\Supmc}{Consortium agreement establishment} A document signed by + \item{}{0}{6}{d}{\Supmc}{Consortium agreement establishment} A document signed by all the partners. \end{livrable} \item This \ST consists of the managment of deliverables. \begin{livrable} - \item{-1-VF}{0}{12}{d}{\Supmc}{First progress report} - \item{-2-VF}{12}{24}{d}{\Supmc}{Second progress report} - \item{-3-VF}{24}{36}{d}{\Supmc}{Final report} + \item{}{0}{12}{d}{\Supmc}{First progress report} + \item{}{12}{24}{d}{\Supmc}{Second progress report} + \item{}{24}{36}{d}{\Supmc}{Final report} \end{livrable} \item This \ST consists of the set up of the web site and iof its managment. \begin{livrable} - \item{-VF}{0}{6}{}{\Supmc}{Web site setting} + \item{}{0}{6}{}{\Supmc}{Web site setting} \end{livrable} \end{workpackage} Index: /anr/task-1.tex =================================================================== --- /anr/task-1.tex (revision 34) +++ /anr/task-1.tex (revision 35) @@ -18,11 +18,11 @@ MPSoC and its 3 targets hardware mapping). \begin{livrable} - \item{-1-V1}{0}{6}{d}{\Supmc}{user manual} + \item{V1}{0}{6}{d}{\Supmc}{user manual} The first milestone of the document for allowing demonstration \ST to start. - \item{-1-V1}{6}{18}{d}{\Supmc}{user manual} + \item{V2}{6}{18}{d}{\Supmc}{user manual} The second milestone takes into account the missing features the demonstrators rise. - \item{-1-VF}{18}{30}{d}{\Supmc}{user manual} + \item{VF}{18}{30}{d}{\Supmc}{user manual} Final release. \end{livrable} @@ -35,15 +35,15 @@ \item This \ST specifies the \xcoach format. \begin{livrable} - \item{-1-V1}{0}{6}{d x}{\Slip}{specification of \xcoach format} + \item{V1}{0}{6}{d x}{\Slip}{specification of \xcoach format} First release of the XML specification of the \xcoach format and its associated documentation allowing to start HLS tools development. - \item{-1-V2}{6}{12}{d x}{\Slip}{specification of \xcoach format} + \item{V2}{6}{12}{d x}{\Slip}{specification of \xcoach format} Second release of XML specification of the \xcoach format taking into account the corrections and modifications that the developers of HLS tools rise. - \item{-1-VF}{12}{18}{d x}{\Slip}{C++ to \xcoach format} + \item{VF}{12}{18}{d x}{\Slip}{C++ to \xcoach format} Release of XML specification of the \xcoach format enhanced with the expression of loop potential. - \item{-2-V1}{0}{12}{x x}{\Subs}{C++ to/from \xcoach format} + \item{V1}{0}{12}{x x}{\Subs}{C++ to/from \xcoach format} The first executable generates a \xcoach description version \taskname-3-V1 from a C++ description of a task defined in \ST @@ -51,17 +51,17 @@ The second program regenerates a C description from a \xcoach description. - \item{-2-VF}{12}{18}{x x}{\Subs}{C++ to/from \xcoach format} + \item{VF}{12}{18}{x x}{\Subs}{C++ to/from \xcoach format} \global\edef\STcTOxcoach{\name} The same programs as the former but for \xcoach format version \name-3-V2. - \item{-3-V1}{0}{18}{x}{\Supmc}{\xcoach format to SystemC} + \item{V1}{0}{18}{x}{\Supmc}{\xcoach format to SystemC} The first release of a program that translates \xcoach description to CABA and TLM-DT SystemC. - \item{-3-VF}{18}{24}{x}{\Supmc}{\xcoach format to SystemC} + \item{VF}{18}{24}{x}{\Supmc}{\xcoach format to SystemC} \global\edef\STxcoachTOsystemc{\name} The \name-3-V1 deliverable without bugs reported by the demonstrators. - \item{-4-V1}{0}{18}{x}{\Subs}{\xcoach format to VHDL} + \item{V1}{0}{18}{x}{\Subs}{\xcoach format to VHDL} The first release of a program that translates \xcoach description to synthesizable VHDL description. - \item{-4-VF}{18}{24}{x}{\Subs}{\xcoach format to VHDL} + \item{VF}{18}{24}{x}{\Subs}{\xcoach format to VHDL} \global\edef\STxcoachTOvhdl{\name} The \name-4-V1 deliverable without bugs reported by the demonstrators. @@ -73,7 +73,7 @@ and by extracting their delays. This is done by using RTL synthesis. \begin{livrable} - \item{-1-VF}{0}{6}{d}{\Subs}{macro-cell definition} + \item{}{0}{6}{d}{\Subs}{macro-cell definition} The document define the macro cell and the file format describing them. - \item{-2-VF}{0}{12}{x}{\Subs}{macro-cell library generator} + \item{}{0}{12}{x}{\Subs}{macro-cell library generator} A progam that generates automatically the characterized macro-cell library for a FPGA device. Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 34) +++ /anr/task-2.tex (revision 35) @@ -25,13 +25,13 @@ \item This \ST corresponds to the Coach System Generator (DSG) software. \begin{livrable} - \item{-V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to + \item{V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to start working using the COACH hardware architecture template. - \item{-V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx + \item{V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx and Altera architectural templates and to the enhanced communication system. - \item{-VF}{0}{36}{x}{\Supmc}{DSG} The final release. + \item{VF}{0}{36}{x}{\Supmc}{DSG} The final release. \end{livrable} \item This \ST relies to the components of the Coach architectural template. \begin{livrable} - \item{-VF}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description + \item{}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description of the SocLib MWMR, TokenRing. \end{livrable} @@ -40,7 +40,7 @@ communication schems. \begin{livrable} - \item{-V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1. - \item{-V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2. - \item{-VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release. + \item{V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1. + \item{V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2. + \item{VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release. \end{livrable} \item This \ST consists of the configuration of the SocLib DNA operating system and the @@ -48,12 +48,12 @@ communication schems. \begin{livrable} - \item{-V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1. - \item{-V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2. - \item{-VF}{0}{36}{x}{\Stima}{DNA OS} The final release. + \item{V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1. + \item{V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2. + \item{VF}{0}{36}{x}{\Stima}{DNA OS} The final release. \end{livrable} \item This \ST relies to definition and implementation of the enhanced communication schems usable in the definition of communicante task graph. \begin{livrable} - \item{-VF}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task + \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task graph inputs (task graph, task description, communication schems). \end{livrable} @@ -61,7 +61,7 @@ architectural template. \begin{livrable} - \item{-1-VF}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and + \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and SystemC model of the MWMR with a PLB bus interface. - \item{-2-VF}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and + \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and SystemC model of the MWMR with an AVALON bus interface. \end{livrable} Index: /anr/task-3.tex =================================================================== --- /anr/task-3.tex (revision 34) +++ /anr/task-3.tex (revision 35) @@ -13,10 +13,10 @@ \mustbecompleted{FIXME:IRISA ........} \begin{livrable} - \item{-V1}{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....} - \item{-VF}{18}{24}{d}{\Sirisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......} + \item{V1}{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....} + \item{VF}{18}{24}{d}{\Sirisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......} \end{livrable} \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt} \begin{livrable} - \item{-V1}{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......} + \item{V1}{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......} \end{livrable} \end{workpackage} Index: /anr/task-4.tex =================================================================== --- /anr/task-4.tex (revision 34) +++ /anr/task-4.tex (revision 35) @@ -30,7 +30,7 @@ them by \xcoach and \xcoachplus drivers. \begin{livrable} - \item{-V1}{6}{12}{x}{\Stima}{UGH integration} An executable that is able to read + \item{V1}{6}{12}{x}{\Stima}{UGH integration} An executable that is able to read \xcoach format. - \item{-VF}{12}{18}{x}{\Stima}{UGH integration} An executable that is able to read + \item{VF}{12}{18}{x}{\Stima}{UGH integration} An executable that is able to read \xcoach format and to write \xcoachplus format. \end{livrable} @@ -39,7 +39,7 @@ them by \xcoach and \xcoachplus drivers. \begin{livrable} - \item{-V1}{6}{12}{x}{\Stima}{GAUT integration} An executable that is able to read + \item{V1}{6}{12}{x}{\Stima}{GAUT integration} An executable that is able to read \xcoach format. - \item{-VF}{12}{18}{x}{\Stima}{GAUT integration} An executable that is able to read + \item{VF}{12}{18}{x}{\Stima}{GAUT integration} An executable that is able to read \xcoach format and to write \xcoachplus format. \end{livrable} @@ -48,14 +48,14 @@ usefull enhancements \begin{livrable} - \item{-1-VF}{18}{24}{x}{\Stima}{UGH enhancement 1} A UGH excutable that is able to treat + \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} A UGH excutable that is able to treat automatically data dominated sections included into a control dominated application. - \item{-2-VF}{21}{27}{x}{\Stima}{UGH enhancement 2} A UGH executable that is able to + \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} A UGH executable that is able to generate an micro-architecture without the varaiable binding currently done by the designer. - \item{-3-VF}{18}{24}{x}{\Supmc}{GAUT enhancement 1} A GAUT excutable that is able to + \item{}{18}{24}{x}{\Supmc}{GAUT enhancement 1} A GAUT excutable that is able to \mustbecompleted{FIXME:UBS: ........}. - \item{-4-VF}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to + \item{}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to \mustbecompleted{FIXME:UBS: ........}. - \item{-5-VF}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to + \item{}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to \mustbecompleted{FIXME:UBS: ........}. \end{livrable} @@ -69,9 +69,9 @@ synthesis. \begin{livrable} - \item{-V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of + \item{V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of the coprocessor frequency calibration. - \item{-V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware + \item{V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware added to the coprocessor to enable the calibration. - \item{-V3}{12}{20}{x}{\Supmc}{frequency calibration} The frequency calibration software + \item{VF}{12}{20}{x}{\Supmc}{frequency calibration} The frequency calibration software consists of a driver in the FPGA-SoC operating system and of a control software on a PC. Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 34) +++ /anr/task-5.tex (revision 35) @@ -39,22 +39,22 @@ part and FPGA-SoC). \begin{livrable} - \item{-1-VF}{0}{21}{x}{\Supmc}{HPC API for Linux PC} - \item{-2-VF}{0}{21}{x}{\Stima}{HPC API for DNA OS} - \item{-3-VF}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} + \item{}{0}{21}{x}{\Supmc}{HPC API for Linux PC} + \item{}{0}{21}{x}{\Stima}{HPC API for DNA OS} + \item{}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} \end{livrable} \item This \ST aims with the implementation of hardware required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx. \begin{livrable} - \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description + \item{}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description of a PLB/VCI bridge. - \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description + \item{}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description of a AVALON/VCI bridge. \end{livrable} \item This \ST aims with the dynamic reconfiguration of FPGA. \begin{livrable} - \item{-1-VF}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers} - \item{-2-VF}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers} - \item{-3-VF}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration} - \item{-3-VF}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration} + \item{}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers} + \item{}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers} + \item{}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration} + \item{}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration} \end{livrable} \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board @@ -62,5 +62,5 @@ They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. \begin{livrable} - \item{-VF}{0}{6}{x}{\Saltera}{HPC development boards} + \item{}{0}{6}{x}{\Saltera}{HPC development boards} \end{livrable} \end{workpackage} Index: /anr/task-6.tex =================================================================== --- /anr/task-6.tex (revision 34) +++ /anr/task-6.tex (revision 35) @@ -18,7 +18,7 @@ or a database management system. \begin{livrable} - \item{-V1}{0}{6}{x}{\Supmc}{reference demonstrator} Choice of the demonstrator and its + \item{V1}{0}{6}{x}{\Supmc}{reference demonstrator} Choice of the demonstrator and its implementation as a PC C/C++ program. - \item{-VF}{0}{12}{x}{\Supmc}{partitionned reference demonstrator} The demonstrator + \item{VF}{0}{12}{x}{\Supmc}{partitionned reference demonstrator} The demonstrator splited into 2 parts, a description as communicante task graph of the FPGA-SoC part. \end{livrable}