Index: anr/task-2.tex
===================================================================
--- anr/task-2.tex	(revision 35)
+++ anr/task-2.tex	(revision 36)
@@ -7,6 +7,7 @@
 \begin{objectif}
 This task relies to the prototyping and the generation of FPGA-SoC digital systems.
-Its is described on figure~\ref{archi-csg} and it consists of
-Its objective is to allows the system designer to explore the system space design by quickly prototyping and then to generate automatically the FPGA-SoC system.
+Its is described on figure~\ref{archi-csg}.
+Its objective is to allow the system designer to explore the system space design by
+quickly prototyping and then to generate automatically the FPGA-SoC system.
 This task consists of
 \begin{itemize}
@@ -14,5 +15,5 @@
 \item the configuration and the development of drivers of the operating systems,
 \item the CSG software that generates the simulators for prototiping and the FPGA-SoC system,
-\item the specification of enhanced communication schem and their sofware and hardware implementation.
+\item the specification of enhanced communication schems and their sofware and hardware implementation.
 \end{itemize}
 This task being based on the SocLib platform, a first release will be delivrable at $T0+12$
@@ -23,47 +24,86 @@
 %
 \begin{workpackage}{D2}
-\item This \ST corresponds to the Coach System Generator (DSG) software.
+\item This \ST corresponds to the Coach System Generator (CSG) software.
     \begin{livrable}
-    \item{V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
-        start working using the COACH hardware architecture template.
-    \item{V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
-        and Altera architectural templates and to the enhanced communication system.
-    \item{VF}{0}{36}{x}{\Supmc}{DSG} The final release.
+    \item{V1}{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
+        The first milestone that will allow demonstrators to start working using the COACH
+        hardware architecture template.
+    \item{V2}{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
+        This milestone adds to CSG the support to the XILINX and ALTERA architectural
+        templates and to the enhanced communication system.
+        In this milestone only the SystemC prototyping will be supported for the XILINX
+        and ALTERA architectural template.
+        HAS is available.
+    \item{V3}{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
+        This milestone extends CSG (\csgPrototypingOnly) to
+        FPGA-SoC generation for the XILINX and ALTERA architectural template.
+    \item{VF}{24}{36}{x}{\Supmc}{CSG} Maintenance work of CSG.
     \end{livrable}
-\item This \ST relies to the components of the Coach architectural template.
+\item This \ST relies to the components of the architectural template.
+    \\
+    For the COACH architectural template, it consists of the devlopment of the VHDL
+    synthesizable description of the missing components. Notice that the SystemC models
+    comes from the SocLib ANR project, the processor with its cache comes from the TSAR
+    ANR project.
+    \\
+    For the XILINX and ALTERA architectural template, we use the XILINX and ALTERA IPs.
+    The component that miss is the MWMR used for commucation between the task of the
+    application.
     \begin{livrable}
-    \item{}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
-        of the SocLib MWMR, TokenRing.
+    \item{}{0}{12}{h}{\Supmc}{COACH architecture} The VHDL synthesizable descriptions
+        of the SocLib MWMR, TokenRing components.
+    \item{V1}{6}{18}{x}{\Stima}{XILINX architecture}
+        \setMacroInAuxFile{csgXilinxSystemC}
+        The SystemC simulation module of the MWMR component with a PLB bus interface plus
+        the SystemC modules of the components of the XILINX architectural template
+        not available in the SocLib component library.
+    \item{VF}{18}{24}{h}{\Stima}{XILINX architecture}
+        The synthesizable VHDL description of the MWMR component corresponding to the
+        SystemC module of the former delivrable (\csgXilinxSystemC).
+    \item{V1}{6}{18}{x}{\Sirisa}{ALTERA architecture}
+        \setMacroInAuxFile{csgAlteraSystemC}
+        The SystemC simulation module of the MWMR component with a AVALON bus interface plus
+        the SystemC modules of the components of the ALTERA architectural template
+        not available in the SocLib component library.
+    \item{VF}{18}{24}{h}{\Sirisa}{ALTERA architecture}
+        The synthesizable VHDL description of the MWMR component corresponding to the
+        SystemC module of the former delivrable (\csgAlteraSystemC);
     \end{livrable}
-\item This \ST consists of the configuration of the SocLib Mutek operating system and the
-    development of drivers for the hardware architectural template and enhanced
-    communication schems.
+\item This \ST consists of the configuration of the SocLib MUTEK and DNA operating
+    system and the development of drivers for the hardware architectural templates
+    and enhanced communication schems defined in \novers{\specCsgManual} delivrable.
+    For the ALTERA and XILINX architectural template, the OSs must also be ported on
+    the NIOS2 and MICROBLAZE processors.
     \begin{livrable}
-    \item{V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
-    \item{V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
-    \item{VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
+    \item{V1}{6}{8}{x}{\Supmc}{MUTEK OS} The drivers required for the first CSG
+    milestone (delivrable \csgCoachArch).
+    \item{V2}{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the
+    second CSG milestone ({\csgPrototypingOnly}).
+    \item{VF}{18}{33}{x}{\Supmc}{MUTEK OS} Maintenance work.
+    \item{}{6}{18}{x}{\upmc}{Port of MUTEK OS}
+        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
+    \item{V1}{6}{8}{x}{\tima}{DNA OS} The drivers required for the first CSG
+    milestone (delivrable \csgCoachArch).
+    \item{V2}{8}{18}{x}{\Stima}{DNA 0S} The drivers required for the
+    second CSG milestone ({\csgPrototypingOnly}).
+    \item{VF}{18}{33}{x}{\Stima}{DNA OS} Maintenance work.
+    \item{}{6}{18}{x}{\tima}{Port of DNA OS}
+        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
     \end{livrable}
-\item This \ST consists of the configuration of the SocLib DNA operating system and the
-    development of drivers for the hardware architectural template and enhanced
-    communication schems.
-    \begin{livrable}
-    \item{V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
-    \item{V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
-    \item{VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
-    \end{livrable}
-\item This \ST relies to definition and implementation of the enhanced communication
-    schems usable in the definition of communicante task graph.
-    \begin{livrable}
-    \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
-        graph inputs (task graph, task description, communication schems). 
-    \end{livrable}
-\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
-    architectural template.
-    \begin{livrable}
-    \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
-        SystemC model of the MWMR with a PLB bus interface.
-    \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
-        SystemC model of the MWMR with an AVALON bus interface.
-    \end{livrable}
+% moved in task 1
+%\item This \ST relies to definition and implementation of the enhanced communication
+%    schems usable in the definition of communicante task graph.
+%    \begin{livrable}
+%    \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
+%        graph inputs (task graph, task description, communication schems). 
+%    \end{livrable}
+%\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
+%    architectural template.
+%    \begin{livrable}
+%    \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
+%        SystemC model of the MWMR with a PLB bus interface.
+%    \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
+%        SystemC model of the MWMR with an AVALON bus interface.
+%    \end{livrable}
 % FIXME:CITI
 \end{workpackage}
