Index: anr/task-5.tex
===================================================================
--- anr/task-5.tex	(revision 35)
+++ anr/task-5.tex	(revision 36)
@@ -29,32 +29,44 @@
     the application part running on the FPGA-SoC.
     \begin{livrable}
-    \item{-VF}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API.
+    \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API.
+        \global\edef\hpcCommApi{\name}
     \end{livrable}
-\item This \ST aims with the application partitioning help. It is a library implementing
-    the communication API with features to profile the application partionning.
+\item This \ST aims consists in helping the application partitioning help.
+    It is a library implementing the communication API with features to profile
+    the application partionning.
     \begin{livrable}
-    \item{-VF}{0}{12}{x}{\Supmc}{HPC partionning help} A library.
+    \item{}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication
+        API defined in the {\hpcCommApi} delivrable.
     \end{livrable}
 \item This \ST aims with the implementation of the communication API on the both sides (PC
     part and FPGA-SoC).
     \begin{livrable}
-    \item{}{0}{21}{x}{\Supmc}{HPC API for Linux PC} 
-    \item{}{0}{21}{x}{\Stima}{HPC API for DNA OS} 
-    \item{}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} 
+    \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API
+        that comminicate with the FPGA-SOC, a library and probably a LINUX module.
+    \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a
+        driver.\global\edef\hpcMutekDriver{\name}
+    \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS.
     \end{livrable}
 \item This \ST aims with the implementation of hardware required by the COACH
     architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
-    \item{}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description
-        of a PLB/VCI bridge.
-    \item{}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description
-        of a AVALON/VCI bridge.
+    \item{}{9}{18}{h}{\Stima}{HPC hardware \xilinx}
+        \setMacroInAuxFile{hpcPlbBridge}
+        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
+    \item{}{9}{18}{h}{\Saltera}{HPC hardware \altera}
+        \setMacroInAuxFile{hpcAvalonBridge}
+        The synthesizable VHDL description of a AVALON/VCI bridge and its corresponding SystemC model.
     \end{livrable}
 \item This \ST aims with the dynamic reconfiguration of FPGA.
     \begin{livrable}
-    \item{}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
-    \item{}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
-    \item{}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
-    \item{}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
+    \item{}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}
+        \global\edef\hpcDynconfDriver{\name}
+        \mustbecompleted{FIXME:TIMA ....}
+    \item{}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}
+        Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS.
+    \item{}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}
+        \mustbecompleted{FIXME:TIMA ....}
+    \item{}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}
+        \mustbecompleted{FIXME:TIMA ....}
     \end{livrable}
 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
@@ -62,5 +74,5 @@
     They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
     \begin{livrable}
-    \item{}{0}{6}{x}{\Saltera}{HPC development boards}
+    \item{}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards.
     \end{livrable}
 \end{workpackage}
