Index: /anr/section-etat-de-art.tex
===================================================================
--- /anr/section-etat-de-art.tex	(revision 368)
+++ /anr/section-etat-de-art.tex	(revision 369)
@@ -19,5 +19,5 @@
 The High-Performance Computing (HPC) world is composed of three main families of architectures:
 many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA.
-The first  two families are dominating the market by taking benefit 
+Today, the first  two families are dominating the market by taking benefit 
 of the strength and influence of mass-market leaders (Intel, Nvidia).
 %such as Intel for many-core CPU and Nvidia for GPGPU.
@@ -26,8 +26,9 @@
 FPGAs architectures enable better performance
 (typically an acceleration factor between 10 and 100)
-while using smaller size and less energy (and heat).
+while using smaller size and less energy (and generating less heat).
 However, using FPGAs presents significant challenges~\cite{hpc06a}.
 First, the operating frequency of an FPGA is low compared to a high-end microprocessor.
-Second, based on Amdahl law,  HPC/FPGA application performance is unusually sensitive 
+Second, % based on Amdahl law,
+ HPC/FPGA application performance is unusually sensitive 
 to the implementation quality~\cite{hpc06b}.
 % Thus, the performance strongly relies on the detected parallelism.
@@ -44,5 +45,6 @@
 researches on HPC-FPGA are mainly conducted in the USA. 
 None of the approaches developed in these researches are fulfilling entirely the
-challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in an FPGA accelerator,
+challenges described above. For example, Convey Computer proposes application-specific instruction 
+set extension of x86 cores in an FPGA accelerator,
 but extension generation is not automated and requires hardware design skills.
 Mitrionics has an elegant solution based on a compute engine specifically
@@ -58,10 +60,15 @@
 appears very interesting for improving HPC performance as well as reducing required area.
 
+%oui, mais il me semble que COACH ne va rien faire à ce sujet. Est-ce la peine de
+%donner des verges pour nous faire battre? En outre, je ne vois pas bien l'intérêt.
+%
+%Paul
+
 \subsubsection{System Synthesis}
 \label{soa:system:synthesis}
 Today, several solutions for system design are proposed and commercialized.
 The existing commercial or free tools do not
-cover the whole system synthesis process in a full automatic way. Moreover,
-they are bound to a particular device family and to IPs library.
+cover the whole system synthesis process in a fully automatic way. Moreover,
+they are bound to a particular device family and to an IP library.
 The most commonly used are provided by \altera and \xilinx to promote their
 FPGA devices. These representative tools used to synthesize SoC on FPGA
@@ -71,8 +78,8 @@
 plug-in to Simulink that enables designers to develop high-performance DSP
 systems for \xilinx FPGAs.
-Designers can design and simulate a system using MATLAB and Simulink. The
+Designers can specify and simulate a system using MATLAB and Simulink. The
 tool will then automatically generate synthesizable Hardware Description
 Language (HDL) code mapped to \xilinx pre-optimized algorithms.
-However, this tool targets onlysignal processing algorithms, \xilinx FPGAs and
+However, this tool targets only signal processing algorithms, \xilinx FPGAs and
 cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
 \\
@@ -80,12 +87,15 @@
 Platform Studio XPS from \xilinx allow to describe a system, to synthesize it, 
 to program it into a target FPGA and to upload a software application.
-Both SOPC Builder and XPS, allow designers to select and parameterize components from 
+Both SOPC Builder and XPS allow designers to select and parameterize components from 
 an extensive drop-down list of IP cores (I/O core, DSP, processor,  bus core, ...) 
-as well as incorporate their own IP. Nevertheless, all the previously introduced tools 
+as well as to incorporate their own IP. Nevertheless, all the previously introduced tools 
 do not provide any facilities to synthesize coprocessors and to simulate the platform 
 at a high level (SystemC). 
-System designer must provide the synthesizable description of its own IP-cores with 
-the feasible bus interface. Design Space Exploration is thus limited
-and SystemC simulation is not possible neither at transactional nor at cycle
+A system designer must provide the synthesizable description of its own IP-cores with 
+a feasible bus interface.%
+%qu'est-ce que c'est qu'un ``feasible bus interface''? a *standard* bus interface? Paul
+%
+Design Space Exploration is thus limited
+and SystemC simulation is not possible either at transactional or at cycle
 accurate level. 
 \\
@@ -121,16 +131,16 @@
 to the HLS input dialect and perform engineering work to exploit the synthesis result 
 at the system level,
-\item Current HLS tools can not target control AND data oriented applications, 
+\item Current HLS tools cannot target control AND data oriented applications, 
 \item HLS tools take into account mainly a unique constraint while realistic design 
 is multi-constrained. 
-Low power consumption constraint which is mandatory for embedded systems is not yet 
+The power consumption constraint which is mandatory for embedded systems is not yet 
 well handled or not handled at all by the HLS tools already available,
-\item The parallelism is extracted from the initial specification.
+\item The parallelism is limited to that present in the initial specification.
 To get more parallelism or to reduce the amount of required memory in the SoC, the user
 must re-write the algorithmic specification while there are techniques such as polyhedral
-transformations to increase the intrinsic parallelism,
+transformations that can automate this process.
 \item While they support limited loop transformations like loop unrolling and loop
 pipelining, current HLS tools do not provide support for design space exploration, either
-through automatic loop transformations or through memory mapping,
+through automatic loop transformations or for improving the memory mapping,
 \item Despite having the same input language (C/C++), they are sensitive to the style in
 which the algorithm is written. Consequently, engineering work is required to swap from 
@@ -159,5 +169,5 @@
 \par
 In this context, ASIP design based on Instruction Set Extensions (ISEs) has 
-received a lot of interest~\cite{NIOS2}, as it makes micro architecture synthesis 
+received a lot of interest~\cite{NIOS2}, as it makes micro-architecture synthesis 
 more tractable \footnote{ISEs rely on a template micro-architecture in which 
 only a small fraction of the architecture has to be specialized}, and help ASIP