Index: /anr/Makefile =================================================================== --- /anr/Makefile (revision 35) +++ /anr/Makefile (revision 36) @@ -4,5 +4,7 @@ section-2.tex section-2.1.tex section-2.2.tex \ flow.pdf section-3.1.tex section-3.2.tex \ - section-4.1.tex \ + task-0.tex task-1.tex task-2.tex task-3.tex \ + task-4.tex task-5.tex task-6.tex \ + section-4.1.tex section-4.4.tex \ architecture-csg.pdf architecture-hls.pdf architecture-hpc.pdf \ dependence-task-h.pdf \ @@ -16,8 +18,9 @@ @$(FIG2DEV) -L pdf -p aaa $< $@ -anr.pdf: $(SOURCES) +anr.pdf: $(SOURCES) gantt.tex gantt @echo "Generating pdf file" @pdflatex anr.tex @bibtex anr + @./gantt < anr.gantt > gantt.tex @pdflatex anr.tex @grep ndefine anr.log @@ -26,4 +29,8 @@ bibtex anr || true -anr.aux: - touch anr.aux +anr.aux gantt.tex: + touch $@ + +gantt: gantt.l + @flex gantt.l && gcc -g lex.yy.c -o gantt + @rm lex.yy.c Index: /anr/anr.sty =================================================================== --- /anr/anr.sty (revision 35) +++ /anr/anr.sty (revision 36) @@ -4,4 +4,22 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%{\catcode`\<=1\catcode`\>=2 +% <\catcode`\{=12\gdef\OBraceTw<{>> +% <\catcode`\}=12\gdef\CBraceTw<}>> +%> +%\@ifundefined{specHasManual}{\let\specHasManual\relax}{} +\let\specHasManual\relax +\let\specCsgManual\relax + +\def\setMacroInAuxFile#1{% + \global\expandafter\edef\csname#1\endcsname{\name} + \expandafter\immediate\expandafter\write\@auxout\expandafter{\expandafter\string\expandafter\gdef\expandafter\string\csname #1\endcsname{\name}} +} +\def\eoa{end-of-args} +\def\@novers#1-#2\eoa{#1} +\def\novers#1{\expandafter\@novers#1\eoa} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\let\ganttlf\relax \newwrite\ganttdata \immediate\openout\ganttdata=anr.gantt @@ -98,9 +116,10 @@ { \let\xcoach\relax + \let\xcoachplus\relax \let\xilinx\relax \let\altera\relax \immediate\write\ganttdata{% T=\the\taskcnt\space S=\the\subtaskcnt\space% - DV=\the\livrablecnt\space BM=##2 EM=##3 TITLE=##6% + D=\the\livrablecnt\space V=##1 BM=##2 EM=##3 TITLE=##6% } } Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 35) +++ /anr/anr.tex (revision 36) @@ -232,4 +232,5 @@ aléas qui risquent de remettre en cause l'aboutissement du projet ainsi que les réunions de projet prévues.\end{itemize}} +\input{section-4.4.tex} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Index: /anr/gantt.l =================================================================== --- /anr/gantt.l (revision 35) +++ /anr/gantt.l (revision 36) @@ -1,3 +1,6 @@ %{ +#define COLOR_Milestone "gtcMilestone" +#define COLOR_BOX_HEAVY "gtcBoxHeavy" +#define COLOR_BOX_LIGHT "gtcBoxLight" #define PICT_TOPSEP 3 @@ -12,26 +15,32 @@ #define TASK_VSEP 2 -#define TASK_BGC0 "red" -#define TASK_BGC1 "yellow" +#define TASK_BGC0 "gtcTaskBG0" +#define TASK_BGC1 "gtcTaskBG1" #define DELIVRABLE_VSEP 1 #define DELIVRABLE_HEIGHT 3 -#define DELIVRABLE_LABELWIDTH 15 +#define DELIVRABLE_LABELWIDTH 10 #define DELIVRABLE_LABELHEIGHT DELIVRABLE_HEIGHT -#define DELIVRABLE_TITLEWIDTH 25 +#define DELIVRABLE_TITLEWIDTH 35 #define DELIVRABLE_TITLEHEIGHT DELIVRABLE_HEIGHT -#define DELIVRABLE_BOXHEIGHT (DELIVRABLE_HEIGHT-2) +#define DELIVRABLE_BOXHEIGHT (DELIVRABLE_HEIGHT) typedef struct _Tlivrable { - int tn,stn,dn; // task, sub-task, number - char v; // 0, 1, 2, ..., F + int tn,stn,dn,vn; // task, sub-task, number + char v; // 0, 1, 2, ..., F char* title; int bm,em; // mois de bebut et de fin - // this fields are filled by the program for data[tn][0][0][0] - int task_line; + // these fields are filled by the program for data[tn][0][0][0] double task_y; // top of task double task_dy; // bot of task is task_y+task_dy - // this fields are filled by the program for data[tn][stn][dn][0] - int del_bm,del_em; // mois de bebut et de fin cummule + // these fields are filled by the program for data[tn][stn][dn][0] + struct _Tlivrable + **vers; // null termiated (vers[i] = &data[tn][stn][dn][i]) + int nbvers; // nombre de vers + double height; // height of livrable + // int del_bm,del_em; // mois de bebut et de fin cummule + // these fields are filled by the program for all elements + int nbTitleLines; + char* titleLines[5]; // null termiated } Tlivrable; @@ -41,4 +50,84 @@ #define V_MAX 10 Tlivrable* data[T_MAX][S_MAX][D_MAX][V_MAX]; + +int milestones[100]; + +char* gen_label_base(char* buf,Tlivrable*p) + { sprintf(buf,"D%d%d%d",p->tn,p->stn,p->dn); return buf; } +char* gen_label_vers(char* buf,Tlivrable*p) + { if (p->nbvers<=1) sprintf(buf,""); else sprintf(buf,"V%c",p->v); return buf; } +char* gen_label_full(char* buf,Tlivrable*p) + { char b[100],v[100]; gen_label_base(b,p); gen_label_vers(v,p); + sprintf(buf,"%s%s%s",b,*v?"-":"",v); return buf; } + +void print_put(double x,double y, const char* object) + { printf("\\put(%.2f,%.2f){%s}\n",x,y,object); } +void print_hline(double x,double y, double len, const char* color) +{ + char object[1024]; + if (color!=0) { printf("\\bgroup\\color{%s}\n",color); } + sprintf(object,"\\line(1,0){%.2f}",len); + print_put(x,y,object); + if (color!=0) { printf("\\egroup\n"); } +} +void print_vline(double x,double y, double len, const char* color) +{ + char object[1024]; + if (color!=0) { printf("\\bgroup\\color{%s}\n",color); } + sprintf(object,"\\line(0,1){%.2f}",len); + print_put(x,y,object); + if (color!=0) { printf("\\egroup\n"); } +} +void print_box( + int filled, char* vers, // vers may be 0, + double x,double y, double dx, double dy, + const char* boxcolor, // may be 0 (default COLOR_BOX_HEAVY) + const char* bgcolor, // may be 0 (not set) + const char* textcolor // may be 0 (black) +){ + double tn=.4; + char object[1024]; + if ( boxcolor==0 ) boxcolor = COLOR_BOX_HEAVY; + if ( filled==1 ) { + sprintf(object, + "\\fcolorbox{black}{%s}{\\makebox(%.2f,%.2f){}}", + boxcolor,dx-2-tn,dy-2-tn); + print_put(x,y+1,object); + } else { + double tn2=tn/2; + double e=.1; + printf("\\bgroup\\color{%s}\n",boxcolor); + printf("\\linethickness{%.2fmm}\n",tn); + print_hline(x+tn2-e ,y, dx ,0); + print_hline(x+tn2-e ,y+dy, dx ,0); + print_vline(x+tn-e ,y+e, dy-2*e ,0); + print_vline(x+dx-2*e,y+e, dy-2*e ,0); + printf("\\egroup\n"); + } + if (vers) { + sprintf(object,"\\begin{tiny}\\textbf{%s}\\end{tiny}",vers); + print_put(x+1,y+.5,object); + } +} + +void gen_titleLines(Tlivrable*p) +{ + const char* macro="\\ganttlf"; + char* pc = p->title; + char* pc2; + + if (pc==0) return; + + while ( (pc2=strstr(pc,macro))!=0 ) { + char c = *pc2; + *pc2 = 0; + p->titleLines[p->nbTitleLines]=strdup(pc); + p->nbTitleLines+=1; + *pc2=c; + pc=pc2+strlen(macro); + } + p->titleLines[p->nbTitleLines]=strdup(pc); + p->nbTitleLines+=1; +} %} @@ -53,8 +142,10 @@ D=[0-9]+ { dn=atoi(yytext+2); } V=V. { v=yytext[3]; } -DV=-VF { dn=0; v='F'; } -DV= { dn=0; v='F'; } -DV=-[0-9]-VF { dn=yytext[4]-'0'; v=yytext[yyleng-1]; } -DV=-[0-9]-V[0-9] { dn=yytext[4]-'0'; v=yytext[yyleng-1]; } +V= { v='F'; } +ML=[0-9]+ { + int i; + for (i=0 ; milestones[i]!=0 ; i++); + milestones[i] = atoi(yytext+3); + } BM=[0-9]+ { bm=atoi(yytext+3); } @@ -62,4 +153,5 @@ TITLE=.*\n { char* pc=yytext+6; + yytext[yyleng-1]=0; while ( *pc==' ' || *pc=='\t' ) pc+=1; title=strdup(pc); @@ -72,9 +164,10 @@ p->bm = bm; p->em = em; + gen_titleLines(p); for (v=0; data[tn][stn][dn][v]!=0 ; v++); data[tn][stn][dn][v] = p; fprintf(stderr,"ADDED: %d %d %d %d\n",tn,stn,dn,v); -{int i,tn=0; fprintf(stderr,"CURR:t=%d:: ",tn); for (i=0; i=S_MAX) break; // shift @@ -127,17 +220,47 @@ } } -fprintf(stderr,"APRES:t=%d:: ",tn,i0,i1); for (i=0; inbvers=0 ; + for (vn=0 ; vnnbvers+=1; + p->vers=(Tlivrable**)malloc(sizeof(*p->vers)*(p->nbvers+1)); + for (vn=0 ; vnnbvers ; vn+=1) { + p->vers[vn] = data[tn][stn][dn][vn]; + data[tn][stn][dn][vn]->nbvers = p->nbvers; + } + p->vers[vn] = 0; + p->height = 1.0*DELIVRABLE_HEIGHT; + if (p->nbTitleLines>=1) { + double h=0; + h += p->vers[p->nbvers-1]->nbTitleLines*DELIVRABLE_TITLEHEIGHT; + h += (p->vers[p->nbvers-1]->nbTitleLines-1)*(DELIVRABLE_TITLEHEIGHT/5.); + if ( h>p->height) p->height=h; + } + } +} + +double task_livrable_height(int tn) +{ +int stn,dn,nblivrables=0; +double height=0; for (stn=0 ; data[tn][stn][0][0]!=0 ; stn++) - for (dn=0 ; data[tn][stn][dn][0]!=0 ; dn++) - for (v=0 ; data[tn][stn][dn][v]!=0 ; v++) - nblignes+=1; - return nblignes; + for (dn=0 ; data[tn][stn][dn][0]!=0 ; dn++) { + nblivrables += 1; + height+=data[tn][stn][dn][0]->height; + } + height += DELIVRABLE_VSEP/2; + height += (nblivrables-1)*DELIVRABLE_VSEP; + height += DELIVRABLE_VSEP/2; + return height; } @@ -148,5 +271,5 @@ const char* color= (tn%2)!=0 ? TASK_BGC1 : TASK_BGC0 ; printf( - "\\put(%.1f,%.1f){\\fcolorbox{black}{%s}{\\makebox(%5.1f,%5.1f){}}}\n", + "\\put(%.2f,%.2f){\\fcolorbox{black}{%s}{\\makebox(%5.2f,%5.2f){}}}\n", 0.0,data[tn][0][0][0]->task_y, color, @@ -170,4 +293,19 @@ } +void print_milestones(double x, double y, double dx, double dy) +{ + int i; + double tn=.3; + //x=x-tn/2; + printf("\\bgroup\n"); + printf("\\color{red}\n"); + printf("\\linethickness{%.2fmm}\n",tn); + for (i=0 ; milestones[i]!=0 ; i+=1) { + double xx= x + milestones[i]*PICT_MONTHWIDTH; + print_vline(xx,y,dy-PICT_MONTHWIDTH-PICT_VSEP,0); + } + printf("\\egroup\n"); +} + double delivrable( double label_x, double box_x, double title_x, @@ -175,4 +313,7 @@ int tn, int stn, int dn) { + Tlivrable* top=data[tn][stn][dn][0]; + Tlivrable* last=data[tn][stn][dn][top->nbvers-1]; + char tmp[1000],label[1000],title[1000]; double y0; int v; @@ -183,25 +324,54 @@ double title_dx = DELIVRABLE_LABELWIDTH ; double title_dy = DELIVRABLE_TITLEHEIGHT ; - for (v=0 ; data[tn][stn][dn][v]!=0 ; v++) { - Tlivrable* l=data[tn][stn][dn][v] ; - y -= DELIVRABLE_HEIGHT; - char label[100]; sprintf(label,"D%d-%d-%d-V%c",tn,stn,dn,l->v); - printf("% Delivrable %d %d %d\n",tn,stn,dn); - y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_LABELHEIGHT)/2; - printf("\\put(%.1f,%.1f)",label_x,y+y0); - printf("{\\makebox(%.1f,%.1f)[l]{\\ganttlabelstyle{%s}}}\n", - label_dx,label_dy,label); - y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_BOXHEIGHT)/2; + +//print_hline(0,y,180,0); + gen_label_base(label,top); + // y -= DELIVRABLE_HEIGHT; + y -= top->height ; +//print_hline(0,y,180,0); + printf("% Delivrable %s (tn=%d stn=%d dn=%d\n",label,tn,stn,dn); + + // print label + //y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_LABELHEIGHT)/2; + y0 = (top->height-DELIVRABLE_LABELHEIGHT)/2; + sprintf(tmp,"\\ganttlabelstyle{%s}",label); + print_put(label_x,y+y0,tmp); + // print title + if (last->nbTitleLines==1) { + y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_TITLEHEIGHT)/2; + y0 += DELIVRABLE_TITLEHEIGHT/5. ; + sprintf(tmp,"\\gantttitlestyle{%s}",last->title); + print_put(title_x,y+y0,tmp); + } else if (last->nbTitleLines>1) { + int i; + // y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_TITLEHEIGHT)/2; + y0=DELIVRABLE_TITLEHEIGHT/5.; + sprintf(tmp,"\\gantttitlestyle{\\shortstack[l]{%s",last->titleLines[0]); + for (i=1 ; inbTitleLines ; i+=1) { + strcat(tmp,"\\\\"); + strcat(tmp,last->titleLines[i]); + } + strcat(tmp,"}}"); + print_put(title_x,y+y0,tmp); + } + + // print box + //y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_BOXHEIGHT)/2; + y0 = (top->height-DELIVRABLE_BOXHEIGHT)/2; + if ( last==top ) { + Tlivrable* l=top; boxx = box_x + l->bm*PICT_MONTHWIDTH ; box_dx = (l->em - l->bm) * PICT_MONTHWIDTH; - printf("\\put(%.1f,%.1f)",boxx,y+y0); - printf("{\\fcolorbox{black}{blue}{\\makebox(%.1f,%.1f){}}}\n", - box_dx-2,box_dy); - y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_TITLEHEIGHT)/2; - printf("\\put(%.1f,%.1f)",title_x,y+y0); - printf("{\\makebox(%.1f,%.1f)[l]{\\gantttitlestyle{%s}}}\n", - title_dx,title_dy,l->title); - y -= DELIVRABLE_VSEP; - } + print_box(1,0,boxx,y+y0,box_dx,box_dy,COLOR_BOX_LIGHT,0,0); + print_box(0,0,boxx,y+y0,box_dx,box_dy,0,0,0); + } else for (v=0 ; vnbvers ; v+=1) { + Tlivrable* l=data[tn][stn][dn][v] ; + gen_label_vers(tmp,l); + boxx = box_x + l->bm*PICT_MONTHWIDTH ; + box_dx = (l->em - l->bm) * PICT_MONTHWIDTH; + print_box(1,0,boxx,y+y0,box_dx,box_dy,COLOR_BOX_LIGHT,0,0); + print_box(0,tmp,boxx,y+y0,box_dx,box_dy,0,0,0); + } + y -= DELIVRABLE_VSEP; return y; } @@ -211,8 +381,9 @@ int stn,dn; double y = data[tn][0][0][0]->task_y+data[tn][0][0][0]->task_dy; + //y += DELIVRABLE_VSEP/2. ; for (stn=0 ; data[tn][stn][0][0]!=0 ; stn++) for (dn=0 ; data[tn][stn][dn][0]!=0 ; dn++) { y=delivrable(label_x,box_x,title_x,y,tn,stn,dn); - } + } } @@ -229,4 +400,5 @@ prepare0(); prepare1(); + prepare2(); pictheight=0 ; @@ -234,10 +406,6 @@ for ( tn=0 ; data[tn][0][0][0]!=0 ; tn++ ); for ( tn=tn-1 ; tn>=0 ; tn-- ) { - int nblines= task_line(tn); data[tn][0][0][0]->task_y = pictheight; - data[tn][0][0][0]->task_line = nblines; - data[tn][0][0][0]->task_dy = 0; - data[tn][0][0][0]->task_dy += nblines*DELIVRABLE_HEIGHT; - data[tn][0][0][0]->task_dy += (nblines-1)*DELIVRABLE_VSEP; + data[tn][0][0][0]->task_dy = task_livrable_height(tn); pictheight += data[tn][0][0][0]->task_dy; pictheight += TASK_VSEP; @@ -268,4 +436,6 @@ task_delivrable(label_x,gantt_x,title_x,tn); } + + print_milestones(gantt_x,0,gantt_dx,gantt_dy+gantt_y); printf("\\end{picture}\n"); Index: /anr/section-4.4.tex =================================================================== --- /anr/section-4.4.tex (revision 35) +++ /anr/section-4.4.tex (revision 36) @@ -1,4 +1,76 @@ +\begin{figure}\leavevmode\center +\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90} +\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99} +\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7} +\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7} +\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4} +\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24} \def\ganttlabelstyle#1{\begin{small}#1\end{small}} \def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}} +\hspace*{-.6cm} \input{gantt.tex} +\caption{\label{gantt}Gantt diagram of delivrables} +\end{figure} +The figure~\ref{gantt} presents the Gantt diagram of the project. +Before the final release (T0+36), there are 4 milestones (red lines on the figure) at +$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent +delivrables. +\begin{description} +\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of + demonstatrors as a referennce software. +\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are + written in COACH. The COACH release allows to prototype and to generate the FPGA-SoC. + The main restrictions are: + 1) only the COACH architectural template is supported, + 2) HAS is not available (but prototyping with virtual coprocessor is available), + 3) Enhanced communication schems are not available. +\item[Milestone 3 ($T0+18$)] The second COACH release. At this step most of the COACH + features are availables. + The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX + architectural template. + The others restriction is that the HAS tools are not yet fully operational. +\item[Milestone 4 ($T0+24$)] The pre-rlease of the COACH project. The full design flow is + supported. + The main restriction are: + 1) The HAS tools are not yet optimum, + 2) dynamic reconfiguration is not supported, + 3) \mustbecompleted{FIXME:ALL .....} +\item[Final Release ($T0+36$)] +\end{description} +This organisation allows to advance globally the project step by step mixing development +and demonstrator delivrables. +So demonstrator feed-back will arrive early and so the risk to point out incompatibility +at the integration phasis is suppressed. +\par +The project has several critical issues: +\begin{description} +\item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToC})] + Because it bonds tightly all the HAS tools, it is a + crucial task. There are no work-arround but as mentionned in + section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we worked ont it since a + year and are confident. +\item[\xcoachplus format (\novers{\specXcoachDoc}, + \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] + It aims with the generation of the coprocessors (hardware \& prototyping model), + By centralizing the coprocessor generations, it guarantees their operating + independently of the used HAS tools. +\item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC}, + {\csgXilinxSystemC}] + The SocLib component library contains most of the SystemC models used for the + prototyping description of the ALTERA and XILINX architectural templates. + Nevertheless, at this time we do'nt know how many are missing and if the existing + are really useables. + If the work of theses tasks is to important, they will be given up. + In this case the work-arround to prototype the XILINX and ALTERA architectural + templates is to use the COACH one. These architectures being very similar, the + simulation results must be proportional. Theses tasks will be changed by measuring + the deviance. +\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})] + If one of these tasks is impossible or too important or leads to inefficiency, + will be given up. + In this case, the COACH architectural template will not be available for HPC and + a SystemC VCI model corresponding to the PCI/X IP will be developped to allow + prototyping. +\end{description} + Index: /anr/task-0.tex =================================================================== --- /anr/task-0.tex (revision 35) +++ /anr/task-0.tex (revision 36) @@ -14,6 +14,8 @@ project. \item To organize the project meetings (every 3 months). -\item To set up the project web site and update it according to the project progress and -dissemination plans. +\item To set up a shared development and dissemination infrastructure as a version control + system version and web site. +\item To ensure the dissemination by providing the COACH releases (milestones and final + release) and their associated installation howto. \end{itemize} \end{objectif} @@ -23,8 +25,9 @@ patners to sign it. \begin{livrable} - \item{}{0}{6}{d}{\Supmc}{Consortium agreement establishment} A document signed by - all the partners. + \item{}{0}{6}{d}{\Supmc}{Consortium agreement} A document discribing the + consortium agreement and signed by all the partners. \end{livrable} -\item This \ST consists of the managment of deliverables. +\item This \ST consists of the managment of deliverables and of the organisation of + project review. \begin{livrable} \item{}{0}{12}{d}{\Supmc}{First progress report} @@ -32,7 +35,13 @@ \item{}{24}{36}{d}{\Supmc}{Final report} \end{livrable} -\item This \ST consists of the set up of the web site and iof its managment. +\item This \ST consists firstly of the set up of the development and dissemination + infrastructure. Then it consists in providing the COACH distribution releases and + in maintaining the dissemination infrastructure. \begin{livrable} - \item{}{0}{6}{}{\Supmc}{Web site setting} + \item{}{0}{6}{}{\Supmc}{infrastructure setup} This task consists of the setup of the + dissemination infrastructure (web site, wiki, faq) and of the setup of the + development infrastructure (version control system configuration). + \item{}{6}{36}{}{\Supmc}{dissemination} This task consists providing the COACH + distribution releases and in maintaining the dissemination infrastructure. \end{livrable} \end{workpackage} Index: /anr/task-1.tex =================================================================== --- /anr/task-1.tex (revision 35) +++ /anr/task-1.tex (revision 36) @@ -13,57 +13,90 @@ \begin{workpackage}{D1} \item This \ST specifies COACH for the system designer. At this - level COACH is a black box. The deliverable is a document allowing the system + level COACH is a black box. The deliverables aredocuments allowing the system designers to use COACH: feeding it (inputs), how to use it (design flow), what COACH can generate (definition of the generic architecture of the MPSoC and its 3 targets hardware mapping). \begin{livrable} - \item{V1}{0}{6}{d}{\Supmc}{user manual} - The first milestone of the document for allowing demonstration - \ST to start. - \item{V2}{6}{18}{d}{\Supmc}{user manual} - The second milestone takes into account the missing features - the demonstrators rise. - \item{VF}{18}{30}{d}{\Supmc}{user manual} - Final release. + \item{V1}{0}{6}{d}{\Supmc}{COACH user manual} \setMacroInAuxFile{specGenManualI} + It is the first milestone of the COACH user manual that will allow demonstrator + \STs to start. + It contains the general description of the framework, the design flow and the + description of the architectural templates. + It refers to the HAS user manual (delivrable {\specHasManual}) and + to the CSG manual (delivrable \specCsgManual) for the COACH input + descriptions. + \item{VF}{6}{12}{d}{\Supmc}{COACH user manual} \setMacroInAuxFile{specGenManual} + The COACH user manual of the \specGenManualI delivrable updated with the feed-backs + of the demonstrator \STs. + \item{V1}{0}{6}{d}{\Stima}{CSG user manual} \setMacroInAuxFile{specCsgManualI} + It is the first milestone of the CSG user manual that will allow demonstrator + \STs to start. + It describes how the task graph is described, the communication schems and its + associated API (Application Programming Interface). + The base is the SRL library and MWMR communication component defined by the SocLib + ANR project. + Nevertheless, these basic schems will be enhanced to allow more efficent + synthesis. + \item{VF}{6}{12}{d}{\Stima}{CSG user manual} \setMacroInAuxFile{specCsgManual} + The CSG user manual of the \specGenManualI delivrable updated with the feed-backs + of the demonstrator \STs. + \item{V1}{0}{6}{d}{\Subs}{HAS user manual} \setMacroInAuxFile{specHasManualI} + It is the first milestone of the HAS user manual that will allow demonstrator + \STs to start. + It describes how tasks of task graph must be written (C/C++ subset) and how + communication schems defined in the {\specCsgManual} delivrable must be described for + coprocessor synthesis. + \item{VF}{6}{12}{d}{\Subs}{HAS user manual} \setMacroInAuxFile{specHasManual} + The HAS user manual of the \specGenManualI delivrable updated with the feed-backs of + the demonstrator \STs. \end{livrable} \item This \ST specifies the software COACH structure. The deliverable is a document listing all the COACH software components and how they cooperate. \begin{livrable} - \item{}{0}{6}{d}{\Supmc}{decription of software architecture} + \item{}{0}{6}{d}{\Supmc}{decription of \ganttlf software architecture} It contains the software list and the data flow among them. \end{livrable} \item This \ST specifies the \xcoach format. \begin{livrable} - \item{V1}{0}{6}{d x}{\Slip}{specification of \xcoach format} - First release of the XML specification of the \xcoach format + \item{V1}{0}{6}{d+x}{\Slip}{specification of \xcoach format} + \setMacroInAuxFile{specXcoachDocI} + First release of the XML specification of the \xcoach format (DTD) and its associated documentation allowing to start HLS tools development. - \item{V2}{6}{12}{d x}{\Slip}{specification of \xcoach format} + \item{V2}{6}{12}{d+x}{\Slip}{specification of \xcoach format} + \setMacroInAuxFile{specXcoachDocII} Second release of XML specification of the \xcoach format taking into account the corrections and modifications that the - developers of HLS tools rise. - \item{VF}{12}{18}{d x}{\Slip}{C++ to \xcoach format} - Release of XML specification of the \xcoach format enhanced with + developers of HAS tools rised. + \item{VF}{12}{18}{d+x}{\Slip}{specification of \xcoach format} + \setMacroInAuxFile{specXcoachDoc} + Last release of XML specification of the \xcoach format enhanced with the expression of loop potential. - \item{V1}{0}{12}{x x}{\Subs}{C++ to/from \xcoach format} - The first executable generates a \xcoach description - version \taskname-3-V1 from a C++ description of a task defined in \ST - \taskname-1. - The second program regenerates a C description from a \xcoach + \item{V1}{6}{12}{x}{\Subs}{C++ to/from \xcoach format} + \setMacroInAuxFile{specXcoachToCI} + This delivrable is composed of 2 softwares. + The first software is a GCC plugin that generates a \xcoach description + (defined in \specXcoachDocI deliverable) from a C++ task description + (defined in \specHasManual deliverable). + The second software regenerates a C description from a \xcoach description. - \item{VF}{12}{18}{x x}{\Subs}{C++ to/from \xcoach format} - \global\edef\STcTOxcoach{\name} - The same programs as the former but for \xcoach format version \name-3-V2. - \item{V1}{0}{18}{x}{\Supmc}{\xcoach format to SystemC} - The first release of a program that translates \xcoach description to CABA - and TLM-DT SystemC. - \item{VF}{18}{24}{x}{\Supmc}{\xcoach format to SystemC} - \global\edef\STxcoachTOsystemc{\name} - The \name-3-V1 deliverable without bugs reported by the demonstrators. - \item{V1}{0}{18}{x}{\Subs}{\xcoach format to VHDL} - The first release of a program that translates \xcoach description to + \item{VF}{12}{18}{x}{\Subs}{C++ to/from \xcoach format} + \setMacroInAuxFile{specXcoachToC} + The same softwares as the former (\specXcoachToCI) but for \xcoach format defined + in the {\specXcoachDoc} deliverable and HAS input defined in the {\specHasManual} + deliverable. + \item{V1}{12}{18}{x}{\Supmc}{\xcoachplus format to SystemC} + \setMacroInAuxFile{specXcoachToSystemCI} + The first release of a program that translates \xcoachplus description to CABA + and TLM-DT SystemC module. + \item{VF}{18}{24}{x}{\Supmc}{\xcoachplus format to SystemC} + \setMacroInAuxFile{specXcoachToSystemC} + Maintenance work of the former software (\specXcoachToSystemCI). + \item{V1}{12}{18}{x}{\Subs}{\xcoachplus format to VHDL} + \setMacroInAuxFile{specXcoachToVhdlI} + The first release of a program that translates \xcoachplus description to synthesizable VHDL description. - \item{VF}{18}{24}{x}{\Subs}{\xcoach format to VHDL} - \global\edef\STxcoachTOvhdl{\name} - The \name-4-V1 deliverable without bugs reported by the demonstrators. + \item{VF}{18}{24}{x}{\Subs}{\xcoachplus format to VHDL} + \setMacroInAuxFile{specXcoachToVhdl} + Maintenance work of the former software (\specXcoachToVhdlI). \end{livrable} \item Backend HLS tools use a characterized macro-cell library to build the @@ -75,5 +108,5 @@ \item{}{0}{6}{d}{\Subs}{macro-cell definition} The document define the macro cell and the file format describing them. - \item{}{0}{12}{x}{\Subs}{macro-cell library generator} + \item{}{6}{12}{x}{\Subs}{macro-cell library generator} A progam that generates automatically the characterized macro-cell library for a FPGA device. Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 35) +++ /anr/task-2.tex (revision 36) @@ -7,6 +7,7 @@ \begin{objectif} This task relies to the prototyping and the generation of FPGA-SoC digital systems. -Its is described on figure~\ref{archi-csg} and it consists of -Its objective is to allows the system designer to explore the system space design by quickly prototyping and then to generate automatically the FPGA-SoC system. +Its is described on figure~\ref{archi-csg}. +Its objective is to allow the system designer to explore the system space design by +quickly prototyping and then to generate automatically the FPGA-SoC system. This task consists of \begin{itemize} @@ -14,5 +15,5 @@ \item the configuration and the development of drivers of the operating systems, \item the CSG software that generates the simulators for prototiping and the FPGA-SoC system, -\item the specification of enhanced communication schem and their sofware and hardware implementation. +\item the specification of enhanced communication schems and their sofware and hardware implementation. \end{itemize} This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ @@ -23,47 +24,86 @@ % \begin{workpackage}{D2} -\item This \ST corresponds to the Coach System Generator (DSG) software. +\item This \ST corresponds to the Coach System Generator (CSG) software. \begin{livrable} - \item{V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to - start working using the COACH hardware architecture template. - \item{V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx - and Altera architectural templates and to the enhanced communication system. - \item{VF}{0}{36}{x}{\Supmc}{DSG} The final release. + \item{V1}{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} + The first milestone that will allow demonstrators to start working using the COACH + hardware architecture template. + \item{V2}{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} + This milestone adds to CSG the support to the XILINX and ALTERA architectural + templates and to the enhanced communication system. + In this milestone only the SystemC prototyping will be supported for the XILINX + and ALTERA architectural template. + HAS is available. + \item{V3}{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} + This milestone extends CSG (\csgPrototypingOnly) to + FPGA-SoC generation for the XILINX and ALTERA architectural template. + \item{VF}{24}{36}{x}{\Supmc}{CSG} Maintenance work of CSG. \end{livrable} -\item This \ST relies to the components of the Coach architectural template. +\item This \ST relies to the components of the architectural template. + \\ + For the COACH architectural template, it consists of the devlopment of the VHDL + synthesizable description of the missing components. Notice that the SystemC models + comes from the SocLib ANR project, the processor with its cache comes from the TSAR + ANR project. + \\ + For the XILINX and ALTERA architectural template, we use the XILINX and ALTERA IPs. + The component that miss is the MWMR used for commucation between the task of the + application. \begin{livrable} - \item{}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description - of the SocLib MWMR, TokenRing. + \item{}{0}{12}{h}{\Supmc}{COACH architecture} The VHDL synthesizable descriptions + of the SocLib MWMR, TokenRing components. + \item{V1}{6}{18}{x}{\Stima}{XILINX architecture} + \setMacroInAuxFile{csgXilinxSystemC} + The SystemC simulation module of the MWMR component with a PLB bus interface plus + the SystemC modules of the components of the XILINX architectural template + not available in the SocLib component library. + \item{VF}{18}{24}{h}{\Stima}{XILINX architecture} + The synthesizable VHDL description of the MWMR component corresponding to the + SystemC module of the former delivrable (\csgXilinxSystemC). + \item{V1}{6}{18}{x}{\Sirisa}{ALTERA architecture} + \setMacroInAuxFile{csgAlteraSystemC} + The SystemC simulation module of the MWMR component with a AVALON bus interface plus + the SystemC modules of the components of the ALTERA architectural template + not available in the SocLib component library. + \item{VF}{18}{24}{h}{\Sirisa}{ALTERA architecture} + The synthesizable VHDL description of the MWMR component corresponding to the + SystemC module of the former delivrable (\csgAlteraSystemC); \end{livrable} -\item This \ST consists of the configuration of the SocLib Mutek operating system and the - development of drivers for the hardware architectural template and enhanced - communication schems. +\item This \ST consists of the configuration of the SocLib MUTEK and DNA operating + system and the development of drivers for the hardware architectural templates + and enhanced communication schems defined in \novers{\specCsgManual} delivrable. + For the ALTERA and XILINX architectural template, the OSs must also be ported on + the NIOS2 and MICROBLAZE processors. \begin{livrable} - \item{V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1. - \item{V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2. - \item{VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release. + \item{V1}{6}{8}{x}{\Supmc}{MUTEK OS} The drivers required for the first CSG + milestone (delivrable \csgCoachArch). + \item{V2}{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the + second CSG milestone ({\csgPrototypingOnly}). + \item{VF}{18}{33}{x}{\Supmc}{MUTEK OS} Maintenance work. + \item{}{6}{18}{x}{\upmc}{Port of MUTEK OS} + Port of MUTEK OS on the NIOS2 and MICROBLAZE processors. + \item{V1}{6}{8}{x}{\tima}{DNA OS} The drivers required for the first CSG + milestone (delivrable \csgCoachArch). + \item{V2}{8}{18}{x}{\Stima}{DNA 0S} The drivers required for the + second CSG milestone ({\csgPrototypingOnly}). + \item{VF}{18}{33}{x}{\Stima}{DNA OS} Maintenance work. + \item{}{6}{18}{x}{\tima}{Port of DNA OS} + Port of MUTEK OS on the NIOS2 and MICROBLAZE processors. \end{livrable} -\item This \ST consists of the configuration of the SocLib DNA operating system and the - development of drivers for the hardware architectural template and enhanced - communication schems. - \begin{livrable} - \item{V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1. - \item{V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2. - \item{VF}{0}{36}{x}{\Stima}{DNA OS} The final release. - \end{livrable} -\item This \ST relies to definition and implementation of the enhanced communication - schems usable in the definition of communicante task graph. - \begin{livrable} - \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task - graph inputs (task graph, task description, communication schems). - \end{livrable} -\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera - architectural template. - \begin{livrable} - \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and - SystemC model of the MWMR with a PLB bus interface. - \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and - SystemC model of the MWMR with an AVALON bus interface. - \end{livrable} +% moved in task 1 +%\item This \ST relies to definition and implementation of the enhanced communication +% schems usable in the definition of communicante task graph. +% \begin{livrable} +% \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task +% graph inputs (task graph, task description, communication schems). +% \end{livrable} +%\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera +% architectural template. +% \begin{livrable} +% \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and +% SystemC model of the MWMR with a PLB bus interface. +% \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and +% SystemC model of the MWMR with an AVALON bus interface. +% \end{livrable} % FIXME:CITI \end{workpackage} Index: /anr/task-4.tex =================================================================== --- /anr/task-4.tex (revision 35) +++ /anr/task-4.tex (revision 36) @@ -13,6 +13,7 @@ \xcoachplus data that is \xcoach format annotated with hardware information such as variable binded on register, operation binded on cell and sheduled. The \xcoach format -being generated by {\STcTOxcoach} \ST and \xcoachplus being treated by {\STxcoachTOsystemc} -and {\STxcoachTOvhdl} \STs, this task is very dependent of task-1 task. +being generated by {\specXcoachToC} deliverable and \xcoachplus being treated by +\novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables, +this task is very dependent of the task~1. \par For the two HAS front-end, this task is based on the already existing HLS tools GAUT and @@ -30,8 +31,9 @@ them by \xcoach and \xcoachplus drivers. \begin{livrable} - \item{V1}{6}{12}{x}{\Stima}{UGH integration} An executable that is able to read + \item{V1}{6}{12}{x}{\Stima}{UGH integration} The UGH software that is able to read \xcoach format. - \item{VF}{12}{18}{x}{\Stima}{UGH integration} An executable that is able to read + \item{V2}{12}{18}{x}{\Supmc}{UGH integration} The UGH software that is able to read \xcoach format and to write \xcoachplus format. + \item{VF}{18}{33}{x}{\Supmc}{UGH integration} Maintenance work of the UGH software. \end{livrable} \item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It @@ -39,7 +41,7 @@ them by \xcoach and \xcoachplus drivers. \begin{livrable} - \item{V1}{6}{12}{x}{\Stima}{GAUT integration} An executable that is able to read + \item{V1}{6}{12}{x}{\Stima}{GAUT integration} The GAUT software that is able to read \xcoach format. - \item{VF}{12}{18}{x}{\Stima}{GAUT integration} An executable that is able to read + \item{VF}{12}{18}{x}{\Stima}{GAUT integration} The GAUT software that is able to read \xcoach format and to write \xcoachplus format. \end{livrable} @@ -48,14 +50,14 @@ usefull enhancements \begin{livrable} - \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} A UGH excutable that is able to treat + \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} The UGH software whith support for treating automatically data dominated sections included into a control dominated application. - \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} A UGH executable that is able to - generate an micro-architecture without the varaiable binding currently done by the + \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} The UGH software that is able to + generate an micro-architecture without the variable binding currently done by the designer. - \item{}{18}{24}{x}{\Supmc}{GAUT enhancement 1} A GAUT excutable that is able to + \item{}{18}{24}{x}{\Subs}{GAUT enhancement 1} A GAUT excutable that is able to \mustbecompleted{FIXME:UBS: ........}. - \item{}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to + \item{}{21}{27}{x}{\Subs}{GAUT enhancement 2} A GAUT excutable that is able to \mustbecompleted{FIXME:UBS: ........}. - \item{}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to + \item{}{21}{27}{x}{\Subs}{GAUT enhancement 2} A GAUT excutable that is able to \mustbecompleted{FIXME:UBS: ........}. \end{livrable} @@ -73,5 +75,5 @@ \item{V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware added to the coprocessor to enable the calibration. - \item{VF}{12}{20}{x}{\Supmc}{frequency calibration} The frequency calibration software + \item{VF}{12}{24}{x}{\Supmc}{frequency calibration} The frequency calibration software consists of a driver in the FPGA-SoC operating system and of a control software on a PC. Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 35) +++ /anr/task-5.tex (revision 36) @@ -29,32 +29,44 @@ the application part running on the FPGA-SoC. \begin{livrable} - \item{-VF}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API. + \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API. + \global\edef\hpcCommApi{\name} \end{livrable} -\item This \ST aims with the application partitioning help. It is a library implementing - the communication API with features to profile the application partionning. +\item This \ST aims consists in helping the application partitioning help. + It is a library implementing the communication API with features to profile + the application partionning. \begin{livrable} - \item{-VF}{0}{12}{x}{\Supmc}{HPC partionning help} A library. + \item{}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication + API defined in the {\hpcCommApi} delivrable. \end{livrable} \item This \ST aims with the implementation of the communication API on the both sides (PC part and FPGA-SoC). \begin{livrable} - \item{}{0}{21}{x}{\Supmc}{HPC API for Linux PC} - \item{}{0}{21}{x}{\Stima}{HPC API for DNA OS} - \item{}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} + \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API + that comminicate with the FPGA-SOC, a library and probably a LINUX module. + \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a + driver.\global\edef\hpcMutekDriver{\name} + \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS. \end{livrable} \item This \ST aims with the implementation of hardware required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx. \begin{livrable} - \item{}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description - of a PLB/VCI bridge. - \item{}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description - of a AVALON/VCI bridge. + \item{}{9}{18}{h}{\Stima}{HPC hardware \xilinx} + \setMacroInAuxFile{hpcPlbBridge} + The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. + \item{}{9}{18}{h}{\Saltera}{HPC hardware \altera} + \setMacroInAuxFile{hpcAvalonBridge} + The synthesizable VHDL description of a AVALON/VCI bridge and its corresponding SystemC model. \end{livrable} \item This \ST aims with the dynamic reconfiguration of FPGA. \begin{livrable} - \item{}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers} - \item{}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers} - \item{}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration} - \item{}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration} + \item{}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers} + \global\edef\hpcDynconfDriver{\name} + \mustbecompleted{FIXME:TIMA ....} + \item{}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers} + Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS. + \item{}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration} + \mustbecompleted{FIXME:TIMA ....} + \item{}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration} + \mustbecompleted{FIXME:TIMA ....} \end{livrable} \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board @@ -62,5 +74,5 @@ They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. \begin{livrable} - \item{}{0}{6}{x}{\Saltera}{HPC development boards} + \item{}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards. \end{livrable} \end{workpackage} Index: /anr/task-6.tex =================================================================== --- /anr/task-6.tex (revision 35) +++ /anr/task-6.tex (revision 36) @@ -18,7 +18,7 @@ or a database management system. \begin{livrable} - \item{V1}{0}{6}{x}{\Supmc}{reference demonstrator} Choice of the demonstrator and its + \item{V1}{0}{6}{x}{\Supmc}{reference demonstrator specification} Choice of the demonstrator and its implementation as a PC C/C++ program. - \item{VF}{0}{12}{x}{\Supmc}{partitionned reference demonstrator} The demonstrator + \item{VF}{6}{12}{x}{\Supmc}{reference demonstrator} The demonstrator splited into 2 parts, a description as communicante task graph of the FPGA-SoC part. \end{livrable}