Index: anr/section-1.tex
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 The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, recent FPGA components, such as the Virtex5-6 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
 \parlf
-Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow. Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both SMES and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest to IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In few years, such chips will surely currently used in embedded systems and even standard general purpose CPU cores will contains a configurable area making explode the low and medium volume markets of digital systems. 
+Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow.%
+%ceci semble vouloir dire que le problÃšme de la HLS est rÃ©solu pour les ASIC, et que ce que COACH veut faire c'est adapter aux 
+%FPGAs. Ca me paraÃ®t Ã  la fois faux et dangereux. Paul
+Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both SMES and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest in IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a few years, such chips will surely be used in embedded systems and even standard general purpose CPU cores will contains a configurable area %
+%incomprÃ©hensible Paul
+making explode the low and medium volume markets of digital systems. 
 \parlf
-COACH is aligned with this long term vision, which requires an integrated design flow for the digital multiprocessors systems, targeting FPGAs and dedicated to the system and software designers; this project donât intend to solve all related issues, but aims at specifying and implementing innovative technological elements of the required tool chain. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application (personal digital assistants , ambient computing components, wireless sensor networks) 2/ mixed systems (CPU + FPGA extension boards) to accelerate a specific application answering High-Performance Computing (HPC) and High-Speed Signal Processing needs, 3/ Sub-system IP to be integrating into a larger system. 
+COACH is aligned with this long term vision, which requires an integrated design flow for the digital multiprocessors systems, targeting FPGAs and dedicated to the system and software designers; this project do not hope to solve all related issues, but aims at specifying and implementing innovative technological elements of the required tool chain. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application (personal digital assistants , ambient computing components, wireless sensor networks) 2/ mixed systems (CPU + FPGA extension boards) to accelerate a specific application answering High-Performance Computing (HPC) and High-Speed Signal Processing needs, 3/ Sub-system IP to be integrating into a larger system. 
 \\
 The COACH open-source environment will integrate several hardware and software technologies:
@@ -11,6 +16,6 @@
 \item Design Space Exploration by allowing to describe an application as a process network i.e. a set of tasks communicating through FIFO channels and to map the application on a shared-memory, MPSoC architecture
 \item High Level Synthesis  of hardware accelerators 
-\item Platform based design: three architectural templates will be provided (free-generic and ALTERA and XILINXâs IPs based)
-\item Hardware/Software communication middleware by implementing an homogeneous HW/SW communication infrastructure and communication APIs, that will be used for communications between software tasks running on embedded processors and dedicated hardware coprocessors
+\item Platform based design: three architectural templates will be provided (free-generic, ALTERA and XILINXâs IPs based)
+\item Hardware/Software communication middleware by implementing an homogeneous HW/SW communication infrastructure and communication API, that will be used for communications between software tasks running on embedded processors and dedicated hardware coprocessors
 \item IP based design: using IP-XACT standard for describing the components of the architectural template and by providing the IP-XACT description of the generated MPSoC
 \end{itemize}
