Index: anr/section-2.tex
===================================================================
--- anr/section-2.tex	(revision 32)
+++ anr/section-2.tex	(revision 38)
@@ -6,11 +6,12 @@
 complexity of design problems. Such methods, addressing these challenges starting from high levels of
 abstraction, will have to perform large solution space explorations both for software and (possibly
-reconfigurable) hrdware, involving almost marginal design effort and offering a high predictability of results
-with respect to cost- and performance- objectives.
+reconfigurable) hardware, reducing the design effort and offering a high predictability of results
+with respect to cost and performance objectives.
 Current design methodologies provide quite low-level abstraction capabilities. However in a few years
 from now tens of programmable processors will be embedded in an IC with more than 100M
-transistors adding to the complexity of the problem of designing such systems. Taking into account
-that the complexity of the software part is increasing at an even faster rate, current solutions for
-design space exploration, mainly manually based, by no means do supply an adequate performance.
+transistors, therefore adding to the complexity of the problem of designing such systems.
+Taking into account that the complexity of the software part is increasing at an even
+faster rate, current solutions for design space exploration, mainly manually based, by no
+means do supply an adequate efficiency.
 Consequently, there is an urgent need to leverage system level
 exploration through the use of a high level specification of the application and an early design
@@ -22,16 +23,16 @@
 \\
 Thus, new system-level design flows need to be developed, enabling the exploration of an application
-independently of the implementation, almost at the beginning of the design process. A
-fundamental element of this evolution is the definition of abstraction layers that should allow the
-systematic re-use of software and hardware components at the system level driven by performance estimation
-and analysis. In this context, COACH will combine modeling and estimation methods and 
-compilers and design space exploration techniques. This approach will cause a real breakthrough in 
-the embedded system design methodology, i.e. one of the radical innovations.
+independently of the implementation, almost at the beginning of the design process.
+A fundamental element of this evolution is the definition of abstraction layers that should allow the
+performance driven re-use of software and hardware components at the system level.
+In this context, COACH will combine modeling and estimation methods and compilers and
+design space exploration techniques. This approach will be a radical innovation in
+embedded system design methodology.
 \\
-The reason is that COACH precedes the use of high-level design tools in the embedded
-systems design flows. In that way, it will make possible a real and efficiently combined
-exploitation of high-level synthesis tools, parallelising approaches and compilers, already
+The reason is that the COACH framework is applied before high-level design tools in the embedded
+systems design flow. In that way, it will make possible a real and efficiently combined
+exploitation of high-level synthesis tools, parallelizing approaches and compilers, already
 available on the market. These tools and approaches are not yet massively adopted, precisely
-because this decisive design step is missing. COACH will indeed permit (i) to predict and
+because this preliminary design step is missing. COACH will indeed permit (i) to predict and
 control implementation optimizations, (ii) to target multiple implementation technologies
 (and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
@@ -43,12 +44,12 @@
 a lower global cost.
 \par
-To get an efficient embedded system, designer has to take into account
-application characteristics when it chooses one of the former technologies.
-This choice is not easy and in most cases designer has to try different
+To get an efficient embedded system, the system designer has to take into account
+application characteristics when it chooses one of the available technologies.
+This choice is not easy and in most cases the designer has to try different
 technologies to retain the most adapted one.
 \\
 The first objective of COACH is to provide an open-source framework to
-design embedded system on FPGA device.
-COACH framework allows designer to explore various software/hardware
+design embedded system on FPGA devices.
+The COACH framework allows the designer to explore various software/hardware
 partitions of the target application, to run timing and functional
 simulations and to generate automatically both the software and the
@@ -65,5 +66,5 @@
 Micro-architectural exploration: When hardware components are required, the
 HLS tools of the framework generate them automatically. At this stage the
-framework provides various HLS tools allowing the micro-architectural space
+framework provides various HLS tools that allow the micro-architectural space
 design exploration. The exploration criteria also are throughput, latency
 and power consumption.
@@ -74,11 +75,11 @@
 
 \item
-Performance measurement: For each point of design space exploration,
-metrics of criteria are available such as throughput, latency, power
+Performance measurement: For each point in the design space,
+figures of merit are available such as throughput, latency, power
 consumption, area, memory allocation and data locality. They are evaluated
-using virtual prototyping, estimation or analysing methodologies.
+using virtual prototyping, estimation or analyzing methodologies.
 \item
-Targeted hardware technology: The COACH description of system is
-independent of the FPGA family.  Every point of the design exploration
+Targeted hardware technology: The COACH description of a system is
+independent of the FPGA family.  Every point of the design
 space can be implemented on any FPGA having the required resources.
 Basically, COACH handles both Altera and Xilinx FPGA families.
@@ -86,12 +87,12 @@
 As an extension of embedded system design, COACH deals also with High
 Performance Computing (HPC).
-In HPC, the kind of targeted application is an existing one running on PC.
-COACH helps designer to accelerate it by migrating critical parts into a
-SoC implemented on a FPGA plugged to the PC bus.
+In HPC, the kind of targeted application is an existing one running on a PC.
+The COACH framework helps designer to accelerate it by migrating critical parts into a
+SoC implemented on an FPGA plugged to the PC bus.
 \par
-COACH is the result of the will of several laboratory to unify their know
-how and skills in the following domains: Operating system and hardware
-communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
-HLS (LIP6, Lab-STIC and LIP).
+COACH is the result of the will of several laboratories to unify their knowhow
+and skills in the following domains: Operating system and hardware
+communication (\tima, \citi), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
+HLS (\upmc, \ubs) and compilation (\irisa, \lip).
 The project objective is to integrate these various domains into a unique
 free framework (licence ...) masking as much as possible these domains and
