Index: /anr/section-1.tex
===================================================================
--- /anr/section-1.tex	(revision 381)
+++ /anr/section-1.tex	(revision 382)
@@ -5,7 +5,18 @@
 %ceci semble vouloir dire que le problÚme de la HLS est résolu pour les ASIC, et que ce que COACH veut faire c'est adapter aux 
 %FPGAs. Ca me paraît à la fois faux et dangereux. Paul
-Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both SMES and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest in IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a few years, such chips will surely be used in embedded systems and even standard general purpose CPU cores will contains a configurable area %
-%incompréhensible Paul
-making explode the low and medium volume markets of digital systems. 
+Unfortunately, ESL tool development today has primarily focused on the design of
+hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
+However, the increasing sophistication of FPGAs has accelerated the need for
+FPGA-based ESL design methodologies. ESL methodologies hold the promise of
+streamlining the design approach by accepting designs written in C/C++ language
+and implementing the function straight into FPGA. Coupling FPGA technologies and
+ESL methodologies will allow both SMES and major companies to design innovative
+devices and to enter new, low and medium volume markets. Furthermore, today
+there is an increasing industrial interest in IC that integrates both hardwired
+CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a
+few years, such chips will surely be used in embedded systems and even standard
+general purpose CPU cores will contains a configurable area.
+This will make possible to target low and medium volume markets of digital
+system and probably explode the indusrial activity of this markets.
 \parlf
 COACH is aligned with this long term vision, which requires an integrated design flow for the digital multiprocessors systems, targeting FPGAs and dedicated to the system and software designers; this project do not hope to solve all related issues, but aims at specifying and implementing innovative technological elements of the required tool chain. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application (personal digital assistants , ambient computing components, wireless sensor networks) 2/ mixed systems (CPU + FPGA extension boards) to accelerate a specific application answering High-Performance Computing (HPC) and High-Speed Signal Processing needs, 3/ Sub-system IP to be integrating into a larger system. 
@@ -24,5 +35,6 @@
 have expressed their interest for this project:
 \altera, FLEXRAS, INPIXAL, CAMKA System, RENESAS Design, EADS-ASTRIUM,
-\mustbecompleted{ ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
+CONTINENTAl,
+\mustbecompleted{ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
 \altera, a major FPGA company provides FPGA cards to the project.
 These companies are either FPGA providers (engaged to collaborate by delivering FPGA board to partners),
Index: /anr/section-2.tex
===================================================================
--- /anr/section-2.tex	(revision 381)
+++ /anr/section-2.tex	(revision 382)
@@ -1,5 +1,5 @@
 Embedded systems (SoC and MPSoC) have become an inevitable evolution in the microelectronic industry.
 The ASIC technology (Application Specific Integrated Circuits) 
-is not an option for markets with small series of products due to ROI. % ROI? Return On Investment? Qu'est-ce que ça vien faire? Paul
+is not an option for markets with small series of products due to RNE costs.
 Fortunately, the new FPGA (Field Programmable Gate Array) components,
 such as the Virtex6 family from \xilinx, or the Stratix4 family from \altera can implement a complete
@@ -67,7 +67,5 @@
 running on a PC.
 The COACH framework helps designers to accelerate it by migrating critical parts into a
-SoC embedded into an FPGA device plugged to the PC PCI/X bus 
-%paul On ne sait jamais, ça pourrait être Hyper Transport
-(or to any other communication fabric).
+SoC embedded into an FPGA device plugged to the PC PCI/X bus.
 \begin{center}\begin{minipage}{.8\linewidth}\label{HPC:definition}\textit{
 The second objective of COACH is to extend the framework for HPC applications.
Index: /anr/section-dissemination.tex
===================================================================
--- /anr/section-dissemination.tex	(revision 381)
+++ /anr/section-dissemination.tex	(revision 382)
@@ -171,4 +171,5 @@
 \letterOfInterest{RENESAS Design}{lettres-2011/Renesas-dossier.jpg},
 \letterOfInterest{EADS-ASTRIUM}{lettres-2011/Astrium.pdf}.
+\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
 %\letterOfInterest{ADACSYS}{lettres-2011/Coach_ADACSYS_lettre_interet},
 %\letterOfInterest{ATEME}{lettres-2011/ATEME.pdf},
Index: /anr/section-etat-de-art.tex
===================================================================
--- /anr/section-etat-de-art.tex	(revision 381)
+++ /anr/section-etat-de-art.tex	(revision 382)
@@ -56,12 +56,4 @@
 Thus, much effort is required to develop design tools that translate high level
 language programs to FPGA configurations.
-Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12}
-(DPR, which enables changing a part of the FPGA, while the rest is still working)
-appears very interesting for improving HPC performance as well as reducing required area.
-
-%oui, mais il me semble que COACH ne va rien faire à ce sujet. Est-ce la peine de
-%donner des verges pour nous faire battre? En outre, je ne vois pas bien l'intérêt.
-%
-%Paul
 
 \subsubsection{System Synthesis}
@@ -92,11 +84,8 @@
 do not provide any facilities to synthesize coprocessors and to simulate the platform 
 at a high level (SystemC). 
-A system designer must provide the synthesizable description of its own IP-cores with 
-a feasible bus interface.%
-%qu'est-ce que c'est qu'un ``feasible bus interface''? a *standard* bus interface? Paul
-%
-Design Space Exploration is thus limited
-and SystemC simulation is not possible either at transactional or at cycle
-accurate level. 
+A system designer must provide the synthesizable description of its own IP-cores
+interfaces it to the SoC bus.
+Design Space Exploration is thus limited and SystemC simulation is not possible
+either at transactional or at cycle accurate level.
 \\
 In addition, \xilinx System Generator, XPS and SOPC Builder are closed world
Index: /anr/section-ressources.tex
===================================================================
--- /anr/section-ressources.tex	(revision 381)
+++ /anr/section-ressources.tex	(revision 382)
@@ -71,5 +71,4 @@
    The effort due to the non permanent personnels is \textbf{#4} \hommemois
    (\textbf{\the\mycnt\%} of the total effort).
-   %All non permanent personnel costs are estimated in \hommemois for senior researchers (post-doc or research engineers).
    The requested funding for non permanent personnels is \textbf{#6\%} of the total ANR
    requested funding.
@@ -88,6 +87,10 @@
 those of annexe~\ref{effort:by:partner:livrable} shows this global effort by partner and
 deliverables.\\
-\textbf{NOTICE:} In these tables and in the following sections the units is the
+\textbf{NOTICE:} 1) In these tables and in the following sections the units is the
 \hommemois of a senior researcher (post-doc or research engineers).
+2) In order to develop and check the FPGA drivers, the partners will by some FPGA boards but
+their costs being less than 4000 \euro, they are not mentionned in the following
+sections.
+
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -163,6 +166,5 @@
   {bull}
   {}
-  {
-    The man power detail in \hommemois by deliverables is given in
+  { The man power detail in \hommemois by deliverables is given in
     annexe~\ref{table-livrables-bull} (page \pageref{table-livrables-bull}).
     and a summary by task in the following table.
@@ -180,7 +182,5 @@
 \ressources
   {thales}
-  { In order to validate the design flow,TRT will buy FPGA developpement boards. The cost
-%check. Paul
-    of each board is less than 4000 k\euro.}
+  {}
   { The man power detail in \hommemois by deliverables is given in
     annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales})