Index: /anr/anr.tex
===================================================================
--- /anr/anr.tex	(revision 45)
+++ /anr/anr.tex	(revision 46)
@@ -21,4 +21,5 @@
 \def\xcoachplus{\texttt{xcoach+}\xspace}
 \def\backbone{backbone infrastructure\xspace}
+\def\Backbone{Backbone infrastructure\xspace}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Index: /anr/section-2.tex
===================================================================
--- /anr/section-2.tex	(revision 45)
+++ /anr/section-2.tex	(revision 46)
@@ -58,5 +58,5 @@
 \begin{itemize} 
 \item
-Design space exploration: It consists in analysing the application runnig
+\textbf{Design space exploration}: It consists in analysing the application runnig
 on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
 hardware/software partitioning of tasks depending on technology choice.
@@ -64,5 +64,5 @@
 consumption criteria.
 \item
-Micro-architectural exploration: When hardware components are required, the
+\textbf{Micro-architectural exploration}: When hardware components are required, the
 HLS tools of the framework generate them automatically. At this stage the
 framework provides various HLS tools that allow the micro-architectural space
@@ -75,10 +75,10 @@
 
 \item
-Performance measurement: For each point in the design space,
+\textbf{Performance measurement}: For each point in the design space,
 figures of merit are available such as throughput, latency, power
 consumption, area, memory allocation and data locality. They are evaluated
 using virtual prototyping, estimation or analyzing methodologies.
 \item
-Targeted hardware technology: The COACH description of a system is
+\textbf{Targeted hardware technology}: The COACH description of a system is
 independent of the FPGA family.  Every point of the design
 space can be implemented on any FPGA having the required resources.
@@ -93,5 +93,5 @@
 COACH is the result of the will of several laboratories to unify their knowhow
 and skills in the following domains: Operating system and hardware
-communication (\tima, \citi), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
+communication (\tima, \upmc), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
 HLS (\upmc, \ubs) and compilation (\irisa, \lip).
 The project objective is to integrate these various domains into a unique
Index: /anr/section-4.1.tex
===================================================================
--- /anr/section-4.1.tex	(revision 45)
+++ /anr/section-4.1.tex	(revision 46)
@@ -69,13 +69,14 @@
 is done through \verb!CSG! (figure~\ref{archi-csg}).
 \vspace*{.75ex}\par
+\mustbecompleted{FIXME == MODIFICATION DE LA FIGURE}
 The project is split into 8 tasks numbered from 0 to 7.
 The first task (task 0) is the project management, the last one (task 7) is
 the dissemination the other task are listed below:
 \begin{enumerate}
-\item\textbf{\backbone:} This task tackles the fundamental points of the
+\item\textbf{\Backbone:} This task tackles the fundamental points of the
 	project such as the defintion of the COACH inputs and outputs,
     the internal formats (e.g. \xcoach), the architectural templates and
     the design flow.
-\item\textbf{system generation:} This task addresses the prototyping and
+\item\textbf{System generation:} This task addresses the prototyping and
     the generation of digital system. Apart from HAS that belong to the task 3
     and 4, its components are those presented figure~\ref{archi-csg}