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 % les objectifs globaux, 
-During the last decades, the design of complex digital systems is more and more reserved to the 
-high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs 
-due to increasing NRE (Non Recurring-Engineering) costs. The market of digital systems is about 
-4,600 M\$ today and is estimated to 5,600 M\$ in 2012.
-Digital system design has been investigated since the eighties for Application 
-Specific Integrated Circuits (ASIC), Digital Signal Processors (DSP) and parallel computing on 
-multiprocessor machines or networks.  Other technologies appeared like Very Large 
-Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP). 
-Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies 
-and thus requieres the design of System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
-Nowadays, Field Programmable Gate Arrays (FPGA), such as the Virtex5 from Xilinx
-or the Stratix4 from Altera, can implement a complete SoC with multiple processors and
-several coprocessors for less than 10K euros per device.
-In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, 
-Co-design, High-Level Synthesis...) is now mature and allow the automation of the design of digital 
-systems and drastically decrease their cost in terms of manpower.
-Thus, coupling both FPGA and ESL methodologies will soon allow small and medium 
-enterprises (SMEs) and major companies to get into new, low and medium volume markets, 
-to design highly innovative devices and to prototype complete digital systems.
-\par
-The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of
-complex digital systems on FPGA devices.  A digital system is an application integrated into one or 
-several chips. These chips can be embedded in devices such as a personal digital assistant (PDA), 
-an ambiant computing component or a wireless sensor network (WSN). They can also be used on a board connected 
-to a PC to accelerate an application as in High-Performance Computing (HPC) or in High-Speed Signal 
-Processing (HSSP).
-
-COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
-K\euro) and drastically reduces them. If proper tools, better suited to
-softaware developers are created, one
-can expect that FPGA based devices 
-will gain market share over Multi-core CPUs and GPUs HPC based solutions.
-Moreover this market can also be boosted by small and even very small new companies
-that will be able to propose embedded system and accelerating solutions for standard
-software applications with acceptable prices.\\
-
-The main idea is to increase the design productivity by selecting a given flexible architectural template 
-and targeting the area of complex digital systems. This project involves the development of methodologies and 
-tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC) 
-of whole systems, while taking into account different application constraints (power consumption, throughput, latency...). 
-The project will also optimize an 
-important interface, usually not taken into account, between the high-level synthesis and the implementation 
-techniques on physical targets and the associated low level tools (logic synthesis and compilation). 
-The design flow will allow, from a high-level specification (written in the C language), to estimate, analyze, optimize the 
-performances and then implement a real architecture. The COACH framework will allow the designer to explore various 
-software/hardware partitioning scenario for the target application through timing and functional simulations and to 
-generate automatically both the software and the synthesizable description of the hardware. 
+The market of digital systems is about 4,600 M$ today and is estimated to
+5,600 M$ in 2012. But the ever growing applications complexity involves
+higher integration of heterogeneous technologies and requires the design of
+complex Multi-Processors System on Chip (MPSoC).
+During the last decade, the design of complex digital ASICs (Application Specific
+Integrated Circuits) appeared to be more and more reserved to high volume markets, because
+the design and fabrication costs of such components exploded, due to increasing NRE (Non
+Recurring-Engineering) costs.
+\\
+FPGA (Field Programmable Gate Array) components, such as the
+Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
+implement a complete MPSoC with multiple processors and several
+coprocessors for few keuros per device.
+In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
+Co-design, High-Level Synthesis...) are now mature and allow the automation of
+a system level design flow that targets FPGA devices.
+We believe that coupling FPGA technologies and ESL methodologies
+will allow both SMEs (Small and Medium Enterprise) and
+major companies to design innovative devices and to enter new, low and
+medium volume markets.
+\\
+The objective of COACH is to provide an integrated design flow, based on the
+SoCLib infrastructure~\cite{soclib}, and optimized for the design of
+multi-processors digital systems targetting FPGA devices.
+Such digital system are generally integrated
+into one or several chips, and there is two types of applications:
+It can be embedded (autonomous) applications
+such as personal digital assistants (PDA), ambiant computing components
+or wireless sensor networks (WSN)
+They can also be extension boards connected to a PC to accelerate a specific computation,
+as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
+\\
+The COACH project fundamental issues are related to design methodologies
+for digital systems, providing estimation, exploration and design tools
+targeting both performance and power optimization at all the abstraction
+levels of the flow (system, architecture, algorithm and logic). 
 
 %verrous scientifiques et techniques
-The main contributions of the project are:
-\begin{itemize} 
-\item Targeted hardware architecture and technology: 
-COACH will handle both Altera and Xilinx FPGA technologies. COACH will define 
-architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
-The parameters of the architectural templates will be the number of CPU, the operating  system...  
-%the coprocessors, the number and the size of the FIFO communication channels 
-Basically, the 3 following architectural templates will be provided:
-\begin{itemize}
-\item A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
-\item An Altera architectural template based on the NIOS and the AVALON bus,
-%FIXME
-% The following point has to be confirmed by XILINX
-% Microblaze+OPB => ARM+Amba ???
-\item A Xilinx architectural template based on the MICROBLAZE and the OPB bus. 
-\end{itemize}
-Moreover, the specification of the application will be independant of both the template 
-architecture and the selected technology. 
-\item Design space exploration: The COACH environment will allow the selection and parametrization of
-the target architecture, the definition of the hardware/software partitioning and the profiling of the application. 
-For each point in the design space, metrics such as throughput, latency, power consumption, 
-silicon area, memory allocation and data locality will be provided.
-This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
-\item Hardware accelerators synthesis (HAS): COACH will allow the automatic generation of hardware accelerators 
-when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and 
-source-level transformations (loop transformations and memory optimisation) will be provided. 
-This will allow further exploration of the micro-architectural design space.
-HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs. 
-data dominated). The HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer.
-\item Communication interface: Coach will define and implement HW/SW communication management and define APIs
-enabling communication between processors, processor/coprocessors,  FPGA and PC.
-\end{itemize}
-%In HPC, the kind of targeted application is an existing one running on PC.
-%COACH helps designer to accelerate it by migrating critical parts into a
-%SoC implemented on a FPGA plugged to the PC bus.\\
-%FIXME licence a speficier
-
-The COACH tools will be designed to hide the hardware as much as possible from the end user.
-It will thus be mainly dedicated to system designers.
-
-
+\vspace*{.9ex}\par
+The COACH environment mixes and integrates several hardware and software technologies.
+The more important technologies are:
+\begin{description}
+\item[Design space exploration]
+    The COACH environment will support design space exploration to help the
+    system designer to select and parameterize the target architecture, and to
+    define the proper hardware/software partitioning of the application.
+    For each point in the design space, metrics such as throughput, latency, power
+    consumption, silicon area, memory allocation and data locality will be provided.
+    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
+    and high-level estimation methodologies.
+\item[Hardware accelerators synthesis (HAS)]
+    COACH will allow the automatic generation of hardware accelerators when required.
+    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
+    (ASIP) design environment and source-level transformation tools (loop transformations
+    and memory optimisation) will be provided.
+    This will allow further exploration of the micro-architectural design space.
+    HLS tools are sensitive to the coding style of the input specification and the domain
+    they target (control vs. data dominated).
+    The HLS tools of COACH will support a common language and coding style to avoid
+    re-engineering by the designer.
+\item[Targeted hardware architecture and technology] 
+    COACH will handle both \altera and \xilinx FPGA devives.
+    COACH will define architectural templates that can be customized by adding
+    dedicated coprocessors and ASIPs and by fixing template parameters such as
+    the number of CPU and the operating system.
+    Basically, the 3 following architectural templates will be provided:
+    \begin{enumerate}
+    \item A Neutral architectural template based on the SoCLib IP core library and the
+      VCI/OCP communication infrastructure.
+    \item An \altera architectural template based on the \altera IP core library and the
+      AVALON system bus.
+    \item A \xilinx architectural template based on the Xlinx IP core library and the OPB
+      system bus.
+    \end{enumerate}
+    Moreover, the specification of the application will be independant of both the
+    architectural template and the target FPGA device.
+\item[Communication interfaces]
+    Coach will define and implement an homogeneous HW/SW communication infrastructure and
+    communication APIs (Application Programming Interface).
+    These laters are on chip communications between processors and coprocessors,
+    and external communications between the FPGA and the host PC. 
+\end{description}
+The COACH design flow will be dedicated to system designers, and will as
+much as possible hide the hardware characteristics to the end user.
+%From the end user point of view, the specification of the application will be
+%independant from both the architectural template and from the selected FPGA
+%family.
 
 % le programme de travail
 \vspace*{.9ex}\par
+%The COACH project targets fundamental issues related to design methodologies for 
+%digital systems by providing estimation, exploration and design tools targeting both 
+%performance and power optimization at all the abstraction levels of the flow (system, 
+%architecture, algorithm and logic).
+To reach this ambitious goal, the project will rely on the experience and the
+complementariness of partners in the following domains:
+Operating system and communication middleware (\tima, \upmc),
+MPSoC architectures (\tima, \ubs, \upmc),
+ASIP architectures (\irisa),
+High Level Synthesis (\tima, \ubs, \upmc) and loop tranformations (\lip).
+\\
+%The CoACH proposal can be described as an extension of the SoCLib virtual
+%prototyping platform to the FPGA technologies.
+The COACH project does not start from scratch.
+It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
+(DSX, component library), operating systems (MutekH, DNA/OS).
+It also leverages on  several existing technologies:
+on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
+on the ROMA~\cite{roma} project for ASIP,
+an the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for loop tranformations,
+and on the \xilinx and \altera IP core libraries.
+Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
+bitstreams.
+\par
+The COACH proposal has been prepared during one year by a technical working group
+involving all the academic partners (one monthly meeting from january 2009 to february
+2010). The objective of these meetings was to analyse the issues of integrating
+and enhancing the formers tools and tecnnologies into a unique framework allowing to both
+virtual prototyping and hardware generation.
+Because the SocLib platform is the base of this project, it may be described as an
+extension of the SoCLib platform.
+\par
+The main development of the COACH project steps are: 
+\begin{enumerate}
+   \item Definition of the end user inputs:
+    The coarse grain parallelism of the application will be described as a communicating
+    task graph, each task being described in C language.
+    Similarly the architectural templates with their parameters and the design constraints
+    will be specified.
+  \item Definition of an internal format for representing task.
+  \item Development of the GCC pluggin for generating the internal format of a
+    C task.
+  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
+    the internal format. This will allow to swap from one tool to another one, and to
+    chain them if necessary.
+  \item Modication of the DSX tool (Design Space eXplorer) of the SocLib
+    platform to generate the bitstream for the various FPGA families and architectural
+    templates.
+  \item Development of new tools such as ASIP compiler, HPC design environment and
+    dynamic reconfiguration of FPGA devices.
+\end{enumerate}
+\par
+The two major FPGA companies \altera and \xilinx are participating to this
+project to support the partners providing the software technologies, and to
+help to generate efficient bitsream for both FPGA families.
+The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
+real use cases to benchmark the COACH design environment.
+\par
+Following the general policy of the SoCLib platform, the COACH project will be an open
+infrastructure, available in the framework of the SoCLib server.
+The architectural templates, and the COACH software tools will be distributed under the
+GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
+IP core library) will be freely available for non commercial use. Commercial licences
+will be negociated for industrial exploitation.
 
-The COACH project targets fundamental issues related to design methodologies for 
-digital systems by providing estimation, exploration and design tools targeting both 
-performance and power optimization at all the abstraction levels of the flow (system, 
-architecture, algorithm and logic).
-
-To reach this ambitious aim, this project will lean on the experience and the complementariness 
-of partners in the following domains: Operating system and hardware
-communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
-HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
-COACH does not start from scratch but relies
-on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
-SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on 
-ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
-
-The project objective is to enhance and seamlessly integrate these tools into
-a unique open source framework. 
-The main steps of this project are:
-1) Definition of the user inputs: application description as set of communicating tasks, each
-task beeing described in the C++ language; architectural template with its parameters; design constraints. 
-2) Definition of the internal \xcoach format for representing a task.
-3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
-4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to 
-swap from one tool to another one and to chain them.
-5) Modification of the Design System eXplorator (DSX) of the SocLib platform to let the user
-explore the design space and then to generate the bitstream.
-%FIXME : a completer
-\par
-
-The two major FPGA companies Altera and Xilinx expect this by supporting
-and participating in this project.
-The role of the industrial partners BULL, THALES, XXX is to provide real
-benchmarks to guide the design of the framework and to prove that COACH is
-usuable and cover a large spectrum of applications.
-
-The COACH arhitectural templates will be freely distributed for non commercial use.
-The software tools of COACH will be developped under the General Public Licence.
-
