Index: /anr/anr.bib =================================================================== --- /anr/anr.bib (revision 55) +++ /anr/anr.bib (revision 56) @@ -4,5 +4,5 @@ @InProceedings{hpc06a, author = {{M.B. Gokhale and al.}}, - title = {{Promises and Pitfalls of Reconfigurable}}, + title = {{Promises and Pitfalls of Reconfigurable Supercomputing}}, booktitle = {Systems and Algorithms, CSREA Press}, pages = {11-20}, @@ -24,4 +24,33 @@ year = {2007}, } +@misc{hpc08, + title = {Mitrionics}, + howpublished = {http://www.mitrionics.com/}, + year = {2009}, +} +@misc{hpc09, + title = {Gidel}, + howpublished = {http://www.gidel.com/}, + year = {2009}, +} +@misc{hpc10, + title = {Convey Computer}, + howpublished = {http://www.conveycomputers.com/}, + year = {2009}, +} +@InProceedings{hpc11, + author = {E. El-Araby, I. Gonzalez and T. El-Ghazawi}, + title = {Virtual Architecture and Design Automation for Partial Reconfiguration }, + booktitle = {HPRCTA}, + year = {2008}, +} +@InProceedings{hpc12, + author = {{P. Lysaght and J. Dunlop}}, + title = {Dynamic Reconfiguration of Field Programmable Gate Arrays}, + booktitle = {Field Programmable Logic and Applications, Oxford, England}, + month = {Sept}, + year = {1993}, +} + % System design Index: /anr/section-2.1.tex =================================================================== --- /anr/section-2.1.tex (revision 55) +++ /anr/section-2.1.tex (revision 56) @@ -95,5 +95,5 @@ to the elimination of huge hardware investment in opposite to ASIC based solution. \\ -This new market may explode in the same way as the micro-computer matket in the eighties. This success was due +This new market may explode in the same way as the micro-computer market in the eighties. This success was due to the low cost of the first micro-processors (compared to main frames) and the advent of high level programming languages which allowed a high number of programmers to launch start-ups in software Index: /anr/section-2.2.tex =================================================================== --- /anr/section-2.2.tex (revision 55) +++ /anr/section-2.2.tex (revision 56) @@ -6,5 +6,5 @@ providing the industry the novel design capabilities enabling them to increase their design productivity with design exploration and synthesis methods that are placed on top -of the stat-of-theart methods, and thus, allowing the industry to better cope with the +of the state-of-the-art methods, and thus, allowing the industry to better cope with the complexity of designed digital systems. \par Index: /anr/section-3.1.tex =================================================================== --- /anr/section-3.1.tex (revision 55) +++ /anr/section-3.1.tex (revision 56) @@ -1,2 +1,5 @@ +% vim:set spell: +% vim:spell spelllang=en: + Our project covers several critical domains in system design in order to achieve high performance computing. Starting from a high level description we aim @@ -4,18 +7,45 @@ \subsubsection{High Performance Computing} -Accelerating high-performance computing (HPC) applications with field-programmable -gate arrays (FPGAs) can potentially improve performance. +% Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language +High-Performance Computing (HPC) world is composed of three main families of architectures: +many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA. +The two first families are dominating the market by taking benefit +of the strength and influence of mass-market leaders (Intel, Nvidia) +%such as Intel for many-core CPU and Nvidia for GPGPU. +In this market, FPGA architectures are emerging and very promising. +By adapting architecture to the software, % (the opposite is done in the others families) +FPGAs architectures enable better performance +(typically between x10 and x100 accelerations) +while using smaller size and less energy (and heat). However, using FPGAs presents significant challenges~\cite{hpc06a}. First, the operating frequency of an FPGA is low compared to a high-end microprocessor. Second, based on Amdahl law, HPC/FPGA application performance is unusually sensitive to the implementation quality~\cite{hpc06b}. -Finally, High-performance computing programmers are a highly sophisticated but scarce -resource. Such programmers are expected to readily use new technology but lack the time -to learn a completely new skill such as logic design~\cite{hpc07a} . -\\ +% Thus, the performance strongly relies on the detected parallelism. +% (pour résumer les 2 derniers points) +Finally, efficient design methodology are required in order to +hide FPGA complexity and the underlying implantation subtleties to HPC users, +so that they don't have to change their habits and can have equivalent design productivity +than in others families~\cite{hpc07a}. + +%état de l'art FPGA HPC/FPGA hardware is only now emerging and in early commercial stages, but these techniques have not yet caught up. +Industrial (Mitrionics~\cite{hpc08}, Gidel~\cite{hpc09}, Convey Computer~\cite{hpc10}) and academic (CHREC) +researches on HPC-FPGA are mainly conducted in the USA. +None of the approaches developed in these researches are fulfilling entirely the +challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator, +but extension generation is not automated and requires hardware design skills. +Mitrionics has an elegant solution based on a compute engine specifically +developed for high-performance execution in FPGAs. Unfortunately, the design flow +is based on a new programming language (mitrionC) implying designer efforts and poor portability. +% tool relying on operator libraries (XtremeData), +% Parle t-on de l'OPenFPGA consortium, dont le but est : "to accelerate the incorporation of reconfigurable computing technology in high-performance and enterprise applications" ? + Thus, much effort is required to develop design tools that translate high level language programs to FPGA configurations. +Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12} +(DPR, which enables changing a part of the FPGA, while the rest is still working) +appears very interesting for improving HPC performance as well as reducing required area. \subsubsection{System Synthesis} Index: /anr/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 55) +++ /anr/section-3.2.tex (revision 56) @@ -82,5 +82,5 @@ RTL IP cores (generic, ALTERA/NIOS/AVALON, XILINX/MICROBLAZE/OPB), one design space exploration tool, -one operating system (OS). +2 operating system (OS). \\ The framework fonctionality will be demonstrated with XXX-EXAMPLE1, XXX-EXAMPLE2 Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 55) +++ /anr/section-4.1.tex (revision 56) @@ -11,4 +11,5 @@ \caption{\label{archi-hpc} software architecture of HPC} \end{figure} +%FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ? % Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} @@ -17,5 +18,5 @@ has to provide. \vspace*{.75ex}\par -For the system genration presented in figure~\ref{archi-csg}, the conductor +For the system generation presented in figure~\ref{archi-csg}, the conductor is the tool \verb!CSG! (COACH System Generator). Its inputs are a process network describing the application to design and the synthesis parameters. @@ -32,5 +33,6 @@ design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the -FPGA device. +FPGA device\footnote{Additional partial bitstreams are generated in case of + dynamic partial reconfiguration}. \\ %To proove CSG that COACH is open and CSG is really configurable, COACH will @@ -65,7 +67,9 @@ other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data through communication primitives (tag 2) implemented in a library. -To evaluate if the relevance of the partitioning, the designer can build a +The relevance of the partitioning is evaluated through a simulator. Once the partitioning is validated, the design of the FPGA part is done through \verb!CSG! (figure~\ref{archi-csg}). + + \vspace*{.75ex}\par \mustbecompleted{FIXME == MODIFICATION DE LA FIGURE} @@ -93,6 +97,7 @@ \item\textbf{Communication between PC \& FPGA-SoC:} This task pools the features dedicated to HPC. The main are the - partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for - both PC and FPGA-SoC sides, the hardware communication components. + partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for + both PC and FPGA-SoC sides, the hardware communication components and + support for dynamic partial reconfiguration. \item\textbf{Demonstrators:} This task groups the demonstrators of the COACH project. Index: /anr/section-4.4.tex =================================================================== --- /anr/section-4.4.tex (revision 55) +++ /anr/section-4.4.tex (revision 56) @@ -47,6 +47,6 @@ supported. The main restriction are: - 1) The HAS tools are not yet optimum, - 2) dynamic reconfiguration is not supported, + 1) The HAS tools have not been yet enhanced, + 2) dynamic partial reconfiguration is not supported, 3) \mustbecompleted{FIXME:ALL .....} \item[Final Release ($T0+36$)] Index: /anr/task-1.tex =================================================================== --- /anr/task-1.tex (revision 55) +++ /anr/task-1.tex (revision 56) @@ -36,5 +36,5 @@ The base is the SRL library and the MWMR communication component defined by the SocLib ANR project. - Nevertheless, these basic schemes will be enhanced to allow more efficent + Nevertheless, these basic schemes will be enhanced to allow more efficient synthesis. \itemL{6}{12}{d}{\Stima}{CSG user manual}{1:0:0} \setMacroInAuxFile{specCsgManual} Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 55) +++ /anr/task-2.tex (revision 56) @@ -14,5 +14,5 @@ \item the development of all the missing components (SytemC model and/or synthesizable VHDL description), \item the configuration and the development of drivers of the operating systems, -\item the CSG software that generates the simulators for prototiping and the FPGA-SoC system, +\item the CSG software that generates the simulators for prototyping and the FPGA-SoC system, \item the specification of enhanced communication schemes and their sofware and hardware implementation. \end{itemize} @@ -106,5 +106,5 @@ Maintenance work. \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{0:0:0} - Port of MUTEK OS on the NIOS2 and MICROBLAZE processors. + Port of DNA OS on the NIOS2 and MICROBLAZE processors. \end{livrable} \end{workpackage} Index: /anr/task-4.tex =================================================================== --- /anr/task-4.tex (revision 55) +++ /anr/task-4.tex (revision 56) @@ -6,5 +6,5 @@ % \begin{objectif} -The objectives of this task are to provide the 2 HAS back-ends of the COACH project and +The objectives of this task are to provide the two HAS back-ends of the COACH project and a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as given by the processors and the BUS. @@ -16,5 +16,5 @@ being generated by \novers{\specXcoachToCA} deliverable and \xcoachplus being treated by \novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables, -this task is very dependen on task~1. +this task is very dependent on task~1. \par For the two HAS front-end, this task is based on the already existing HLS tools GAUT and @@ -29,5 +29,5 @@ \begin{workpackage} \item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It - consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing + consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing them by \xcoach and \xcoachplus drivers. \begin{livrable} Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 55) +++ /anr/task-5.tex (revision 56) @@ -1,2 +1,5 @@ +% vim:set spell: +% vim:spell spelllang=en: + \begin{taskinfo} \let\UPMC\leader @@ -10,11 +13,12 @@ \begin{itemize} \item Helping the HPC designer to find a good partition of the initial application - (figure~\ref{archi-hpc}. -\item Providing communication schemes between the software part runing on the PC and the + (figure~\ref{archi-hpc}). +\item Providing communication schemes between the software part running on the PC and the FPGA-SoC. \item Implementing the communication scheme at all levels: partition help, software implementation both on the PC and in the operating system of the FPGA-SoC, hardware. -\item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA} +\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order to optimize FPGA ressource usage. \end{itemize} + The low level hardware transmission support will be the PCI/X bus which allows high bit-rate transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for @@ -22,4 +26,6 @@ This will allow us at least to be inspired by GPU communication schemes and may be to reuse parts of the GPU softwares. + + \end{objectif} % @@ -31,9 +37,12 @@ \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0} \setMacroInAuxFile{hpcCommApi} - User refernce manual describing the API. + User reference manual describing the API. \end{livrable} -\item This \ST consists in helping to partition the application. +\item This \ST consists in helping to partition applications. It is a library implementing the communication API with features to profile the partitioned application. +%FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application. +% It is a profiling (or simulation) library implementing the communication API + \begin{livrable} \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} @@ -52,5 +61,5 @@ Port of the {\hpcMutekDriver} driver on the DNA OS. \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} - Maintenance work of HPC API for both Lunix PC and MUTEK OS. + Maintenance work of HPC API for both Linux PC and MUTEK OS. \end{livrable} \item This \ST deals with the implementation of hardware required by the COACH @@ -64,16 +73,21 @@ The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. \end{livrable} -\item This \ST deals with the dynamic reconfiguration of an FPGA. +\item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. +It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. + \begin{livrable} + \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration} + Extension of the \xilinx architectural template ({\csgAllArch}) +in order to integrate dynamic partial reconfiguration regions. +Modification of CSG software to support the extended \xilinx template. \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0} \setMacroInAuxFile{hpcDynconfDriver} - \mustbecompleted{FIXME:TIMA ....} + The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA. \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1} - Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS. - \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2} - \mustbecompleted{FIXME:TIMA ....} - \itemL{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}{0:0:0} - \mustbecompleted{FIXME:TIMA ....} - \end{livrable} + Port of the {\hpcDynconfDriver} drivers on the MUTEK OS. + \itemL{18}{36}{x}{\Stima}{HPC support for \ganttlf dynamic reconfiguration}{0:0:2} +Extension of the HPC partionning helper in order to integrate dynamic partial reconfiguration dedicated features +(reconfiguration time of regions, variable number of coprocessors) +\end{livrable} \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board with its PCI/X IP. These boards are dedicated to the COACH HPC development.