Changeset 62 for anr

Timestamp:

Feb 2, 2010, 6:04:04 PM (15 years ago)

Author:

alain

Message:

Introducing content in sections 5 & 6

Location:

anr

Files:

• anr.tex (modified) (2 diffs)
• section-5.tex (modified) (1 diff)
• section-6.1.tex (modified) (1 diff)
• section-6.2.tex (modified) (1 diff)

anr/anr.tex

@@ -13 +13 @@
 \usepackage{xspace}
 \usepackage{geometry}
+\usepackage{textcomp}
 \geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=3cm}
 
@@ -280 +281 @@
 
 \subsection{Relevant experience of the project coordinator}
-\anrdoc{(0,5 page maximum) Fournir les éléments permettant de juger la
-capacité du coordinateur à coordonner le projet.}
 \input{section-6.2.tex}
 

anr/section-5.tex

@@ +1 @@
+\subsection{Dissemination}
+
+The Coach project will bring new scientific results in various fields, such as high level synthesis,
+hardware/software codesign, virtual prototyping, harware oriented compilation technics,
+automatic parallelisation, etc. These results will be presented in the relevant International
+Conferences, namely DATE, DAC, or ICCAD. 
+
+More generally, the Coach infrastructure and the design flow supported by the Coach
+tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
+in various worshops and conferences.
+
+Following the general policy of the SoCLib platform, the COACH project will be an 
+open infrastructure, and the Coach tools and libraries will available in the framework 
+of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. 
+
+\subsection{Exploitation of results}
+
+The main goal of the Coach project is to help SMEs (Small and Medium Enterprises) 
+to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
+Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
+As the fabrication costs of an ASIC is generally too high for SMEs, the Coach project focus
+on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) 
+tools is an issue, and the Coach project will follow the same general policy as the SoCLib platform :
+
+\begin{itemize}
+\item
+All software tools supporting the Coach design flow will be available as free software.
+All academic partners contributing to the Coach project agreed to distribute the ESL software
+tools under the same GPL license as the SoCLib tools.  
+\item
+The SystemC simulation modelsafor the hardware components
+used by the SoCLib architectural template will be distributed as free software 
+under a non-contaminant LGPL license.
+\item
+The synthesizable VHDL models supporting the neutral architectural template
+(corresponding to the SocLib IP cores library), will have two modes of dissemination.
+A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
+also general purpose, reusable components, such as processor cores, memory controllers
+optimised cache controllers, peripheral controllers, or bus controllers.
+For non commercial use (i.e. research or education in an academic context,  
+or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
+For commercial use, commercial licenses will be negociated between the owners and the customers.
+\item
+The proprietary ALTERA and XILINX IP core libraries are commercial products
+that are not involved by the free software policy, but these libraries will be supported by the 
+synthesis tools developped in the Coach project.
+\end{itemize}
+
+This general approach is supported by a large number of SMEs, as demonstrated by the "letters
+of interest" that have been collected during the preparation of the project :
+\begin{itemize}
+\item 
+\item
+\item
+\item
+\item
+\end{itemize}
+
+\subsection{Management of Intellectual Property}
+
+A global consortium agreement will be defined during the first six monts of the project.
+As already stated, the Coach project has been prepared during one tear by a monthly meeting 
+involving the five academic partners. The general free software policy described in the 
+previous section has been agreed by academic partners  and has been
+approved by all industrial participants. This free software policy will 
+simplify the definition of the consortium agreement.
+

anr/section-6.1.tex

@@ -23 +23 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\upmc}
+University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students). 
+The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
+more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). 
+The « System on Chip » Department of LIP6 consists of  80 people, including 40 PHD students. 
+The research focus on CAD tools and methods for VLSI and System on Chip design. 
+The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. 
+The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, 
+OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. 
+The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
+The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
+the SoCLib WEB server. The LIP6 will be in charge of integrating the Coach results in the frame work of
+the SoCLib infrastructure to provide an open access to the Coach design environment.
+Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis, 
+and the DSX tool for design space exploration, that will be two building blocks for the Coach design-flow.
+Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
+(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies 
+(including FLEXRAS) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

anr/section-6.2.tex

@@ +1 @@
+The Coach project will be coordinated by the Professor Alain Greiner from 
+Université Pierre et Marie Curie.
+Alain Greiner is the initiator and the main architect of the SoCLib project.
+This ANR plat-form for virtual prototyping of MPSoCs involved 6 industrial companies 
+(including ST Microelectronics and Thales) and ten academic laboratories 
+(5 of them are involved in the Coach project).
+The SoCLib project was managed by Thales, but the technical coordination has been done
+by Alain Greiner, that has a good experience in coordinating large technical projects
+in both industrial and academic contexts:
+
+\begin {itemize}
+\item 
+He received the "Docteur es Sciences" degree from University Denis DIDEROT
+in 1982 after working six years at Commissariat a l' Energie Atomique.
+\item
+From 1986 to 1990, he worked for the french BULL company, as team leader,
+in charge of designing the Basic Processing Unit for the BULL 
+DPS7000 computer, the most powerfull mainframe from the family.
+\item
+In 1990, Alain Greiner joined UPMC, as Professor and became the head of the
+MASI laboratory in 1994. From 2000, he was the head of the Hardware Department
+of the LIP6 laboratory.
+\item
+From 1990 to 2000, he was the leader of the the ALLIANCE project: This GPL based
+cooperative project developped a public domain VLSI/CAD system that has been used 
+in more than 200 universities worlwide, for education and research.
+This project obtained the Seymour Cray award in 1994.
+\end {itemize}
+
+