Index: anr/anr.bib
===================================================================
--- anr/anr.bib	(revision 61)
+++ anr/anr.bib	(revision 77)
@@ -91,11 +91,4 @@
 }
 
-@INBOOK{gaut08,
-  author    = {P. Coussy and al.},
-  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
-  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
-  publisher = {Springer},
-  year      = {2008},
-}
 
 @INBOOK{ugh08,
@@ -125,4 +118,176 @@
   year         = {2009},
 }
+
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%% UBS
+
+
+@INBOOK{gaut08,
+  author    = {P. Coussy and al.},
+  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
+  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
+  publisher = {Springer},
+  year      = {2008},
+}
+
+@article{DBLP:journals/dt/CoussyT09,
+  author    = {Philippe Coussy and
+               Andres Takach},
+  title     = {Guest Editors' Introduction: Raising the Abstraction Level
+               of Hardware Design},
+  journal   = {IEEE Design {\&} Test of Computers},
+  volume    = {26},
+  number    = {4},
+  year      = {2009},
+  pages     = {4-6},
+  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
+  bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+
+@article{DBLP:journals/dt/CoussyGMT09,
+  author    = {Philippe Coussy and
+               Daniel D. Gajski and
+               Michael Meredith and
+               Andres Takach},
+  title     = {An Introduction to High-Level Synthesis},
+  journal   = {IEEE Design {\&} Test of Computers},
+  volume    = {26},
+  number    = {4},
+  year      = {2009},
+  pages     = {8-17},
+  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
+  bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+
+@article{DBLP:journals/vlsisp/ThabetCHM09,
+  author    = {Farhat Thabet and
+               Philippe Coussy and
+               Dominique Heller and
+               Eric Martin},
+  title     = {Exploration and Rapid Prototyping of DSP Applications using
+               SystemC Behavioral Simulation and High-level Synthesis},
+  journal   = {Signal Processing Systems},
+  volume    = {56},
+  number    = {2-3},
+  year      = {2009},
+  pages     = {167-186},
+  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
+  bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+
+
+@inproceedings{CHAVET:2007:HAL-00153994:1,
+	title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
+	author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
+	abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
+	language = {{A}nglais},
+	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
+	booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
+	publisher = {{L}ibrary of {C}ongress },
+	pages = {2946 },
+	address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
+	editor = {{IEEE} },
+	note = {{ISBN}:1-4244-0921-7 },
+	audience = {internationale },
+    day = {28},
+    month = {05},
+    year = {2007},
+    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
+    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
+}
+
+
+@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
+  author    = {Cyrille Chavet and
+               Caaliph Andriamisaina and
+               Philippe Coussy and
+               Emmanuel Casseau and
+               Emmanuel Juin and
+               Pascal Urard and
+               Eric Martin},
+  title     = {A design flow dedicated to multi-mode architectures for
+               DSP applications},
+  booktitle = {ICCAD},
+  year      = {2007},
+  pages     = {604-611},
+  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
+  crossref  = {DBLP:conf/iccad/2007},
+  bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+
+@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
+  author    = {Cyrille Chavet and
+               Philippe Coussy and
+               Pascal Urard and
+               Eric Martin},
+  title     = {A design methodology for space-time adapter},
+  booktitle = {ACM Great Lakes Symposium on VLSI},
+  year      = {2007},
+  pages     = {347-352},
+  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
+  crossref  = {DBLP:conf/glvlsi/2007},
+  bibsource = {DBLP, http://dblp.uni-trier.de}
+}
+
+
+@inproceedings{CHAVET:2007:HAL-00154025:1,
+	title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
+	author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
+	abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
+	language = {{A}nglais},
+	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
+	booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
+	publisher = {{E}urasip },
+	pages = {??? },
+	address = {{P}oznan {P}ologne },
+	audience = {internationale },
+    day = {03},
+    month = {09},
+    year = {2007},
+    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
+    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
+}
+
+
+@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
+	title = { {S}ynthesis of {M}ultimode digital signal processing systems},
+	author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
+	abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
+	language = {{A}nglais},
+	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
+	booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
+	publisher = {{AHS} },
+	pages = {7 },
+	address = {{E}dinburgh {R}oyaume-{U}ni },
+	audience = {internationale },
+    year = {2007},
+    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
+    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
+}
+
+
+@inproceedings{COUSSY:2005:HAL-00077301:1,
+	title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
+	author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
+	abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
+	keywords = {{DSP} application, synthesis under memory and communication constraints},
+	language = {{A}nglais},
+	affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
+	booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
+	publisher = {{IEEE} },
+	pages = {{V}ol. {V} p. 61-64 },
+	editor = {{IEEEE} },
+    year = {2005},
+    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
+    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
+}
+
+
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
