Changeset 85

Timestamp:

Feb 3, 2010, 6:21:19 PM (15 years ago)

Author:

coach

Message:

Completed ST4-1 and ST4-2

File:

• anr/task-3.tex (modified) (1 diff)

anr/task-3.tex

@@ -17 +17 @@
 %
 \begin{workpackage}
-  \item Extraction de motifs et regénération au format COACH annoté
-    \mustbecompleted{FIXME:IRISA ........}
+  \item This sub-task aims at providing compiler support for custom instructions 
+  within the HAS front-end. It will take as input the COACH intermediate 
+  representation, and will output an annotated COACH representation containing the custom
+  instructions definitions and their occurence in the application.
+
     \begin{livrable}
-      \itemV{0}{18}{d}{\Sirisa}{Interation manuelle des motifs}
-        \mustbecompleted{FIXME .....}
-      \itemL{18}{24}{d}{\Sirisa}{Integration manuelle des motifs}{0:0:0}
-        \mustbecompleted{FIXME ......}
+      \itemV{0}{18}{d}{\Sirisa}{Instruction selection for user defined custom instructions}
+        In this first version of the software, the computations patterns corresponding to
+        custom instruction are specified by the user, and then automatically extracted from 
+        the application intermediare representation. 
+        %\mustbecompleted{FIXME .....}
+      \itemL{18}{24}{d}{\Sirisa}{Automatic extraction of patterns}{0:0:0}
+        In this second version, the software will also be able to automatically indentify 
+        interesting pattern candidates in the application code, and use them as custom 
+        instructions.  
     \end{livrable}
-  \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
+ 
+ \item In this sub-task, we provide micro-architectural template models for the two target
+ processor architectures (NIOS-II and MIPS) supported within in the COACH-ASIP design flow. 
+ For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 
+ of the architecture, along with its architectural extensions 
     \begin{livrable}
-        \itemL{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs}{0:0:0}
-        \mustbecompleted{FIXME ......}
+      \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple extensible MIPS architectural template}
+      \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple extensible MIPS architectural template}
+                %\mustbecompleted{FIXME .....}
+      \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0}
+
+      \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a extensible MIPS with tight
+      architecural integration of its instruction set extensions}
+      \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a extensible MIPS with tight
+      architecural integration of its instruction set extensions}
+      \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0}
+
     \end{livrable}
-  \item Extraction of parallelism in polyhedral loops and conversion
-    into a process network.
+
+  \item Extraction of parallelism in polyhedral loops and conversion into a process network.
+
    \begin{livrable}
     \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}