Changeset 85


Ignore:
Timestamp:
Feb 3, 2010, 6:21:19 PM (15 years ago)
Author:
coach
Message:

Completed ST4-1 and ST4-2

File:
1 edited

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  • anr/task-3.tex

    r84 r85  
    1717%
    1818\begin{workpackage}
    19   \item Extraction de motifs et regénération au format COACH annoté
    20     \mustbecompleted{FIXME:IRISA ........}
     19  \item This sub-task aims at providing compiler support for custom instructions
     20  within the HAS front-end. It will take as input the COACH intermediate
     21  representation, and will output an annotated COACH representation containing the custom
     22  instructions definitions and their occurence in the application.
     23
    2124    \begin{livrable}
    22       \itemV{0}{18}{d}{\Sirisa}{Interation manuelle des motifs}
    23         \mustbecompleted{FIXME .....}
    24       \itemL{18}{24}{d}{\Sirisa}{Integration manuelle des motifs}{0:0:0}
    25         \mustbecompleted{FIXME ......}
     25      \itemV{0}{18}{d}{\Sirisa}{Instruction selection for user defined custom instructions}
     26        In this first version of the software, the computations patterns corresponding to
     27        custom instruction are specified by the user, and then automatically extracted from
     28        the application intermediare representation.
     29        %\mustbecompleted{FIXME .....}
     30      \itemL{18}{24}{d}{\Sirisa}{Automatic extraction of patterns}{0:0:0}
     31        In this second version, the software will also be able to automatically indentify
     32        interesting pattern candidates in the application code, and use them as custom
     33        instructions. 
    2634    \end{livrable}
    27   \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
     35 
     36 \item In this sub-task, we provide micro-architectural template models for the two target
     37 processor architectures (NIOS-II and MIPS) supported within in the COACH-ASIP design flow.
     38 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL)
     39 of the architecture, along with its architectural extensions
    2840    \begin{livrable}
    29         \itemL{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs}{0:0:0}
    30         \mustbecompleted{FIXME ......}
     41      \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple extensible MIPS architectural template}
     42      \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple extensible MIPS architectural template}
     43                %\mustbecompleted{FIXME .....}
     44      \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0}
     45
     46      \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a extensible MIPS with tight
     47      architecural integration of its instruction set extensions}
     48      \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a extensible MIPS with tight
     49      architecural integration of its instruction set extensions}
     50      \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0}
     51
    3152    \end{livrable}
    32   \item Extraction of parallelism in polyhedral loops and conversion
    33     into a process network.
     53
     54  \item Extraction of parallelism in polyhedral loops and conversion into a process network.
     55
    3456   \begin{livrable}
    3557    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
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