Index: /anr/task-3.tex
===================================================================
--- /anr/task-3.tex	(revision 85)
+++ /anr/task-3.tex	(revision 86)
@@ -19,15 +19,15 @@
   \item This sub-task aims at providing compiler support for custom instructions 
   within the HAS front-end. It will take as input the COACH intermediate 
-  representation, and will output an annotated COACH representation containing the custom
-  instructions definitions and their occurence in the application.
+  representation, and will output an annotated COACH IR containing the custom
+  instructions definitions along with their occurrence in the application.
 
     \begin{livrable}
       \itemV{0}{18}{d}{\Sirisa}{Instruction selection for user defined custom instructions}
         In this first version of the software, the computations patterns corresponding to
-        custom instruction are specified by the user, and then automatically extracted from 
-        the application intermediare representation. 
+        custom instruction are specified by the user, and then automatically extracted (when
+        beneficial) from the application intermediate representation. 
         %\mustbecompleted{FIXME .....}
       \itemL{18}{24}{d}{\Sirisa}{Automatic extraction of patterns}{0:0:0}
-        In this second version, the software will also be able to automatically indentify 
+        In this second version, the software will also be able to automatically identify 
         interesting pattern candidates in the application code, and use them as custom 
         instructions.  
@@ -45,7 +45,7 @@
 
       \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a extensible MIPS with tight
-      architecural integration of its instruction set extensions}
+      architectural integration of its instruction set extensions}
       \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a extensible MIPS with tight
-      architecural integration of its instruction set extensions}
+      architectural integration of its instruction set extensions}
       \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0}
 
@@ -61,5 +61,5 @@
     \itemV{6}{12}{x}{\Slip}{Process Construction)}
       Preliminary implementation in the Syntol framework. 
-      At this step the sofware will just implement a single constructor.
+      At this step the software will just implement a single constructor.
     \itemV{12}{18}{x}{\Slip} {Arrays and FIFO}
       Implementation of the array contraction and FIFO construction algorithm. 
@@ -68,5 +68,5 @@
       Extension of automatic parallelization and array contraction
       to non-polyhedral loops.
-    \itemL{30}{36}{x}{\Slip} {Process ans FIFO Construction} {0:0:0}
+    \itemL{30}{36}{x}{\Slip} {Process and FIFO Construction} {0:0:0}
       Final release taking into account the feedbacks from the 
       demonstrator \STs.