Index: /anr/anr.bib =================================================================== --- /anr/anr.bib (revision 92) +++ /anr/anr.bib (revision 93) @@ -74,5 +74,5 @@ @InProceedings{disydent05, - author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, François Donnet and Pascal Gomez}}, + author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}}, title = {{Platform-based design from parallel C specifications}}, booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems}, @@ -496,2 +496,89 @@ publisher = {ACM} } + + + +%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%% + +@inproceedings{DAC09, + author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo}, + title = {Way Stealing: cache-assisted automatic instruction set extensions}, + booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference}, + year = {2009}, + isbn = {978-1-60558-497-3}, + pages = {31--36}, + location = {San Francisco, California}, + doi = {http://doi.acm.org/10.1145/1629911.1629923}, + publisher = {ACM}, + address = {New York, NY, USA}, + } + +@inproceedings{CODES08, + author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo}, + title = {Speculative DMA for architecturally visible storage in instruction set extensions}, + booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis}, + year = {2008}, + isbn = {978-1-60558-470-6}, + pages = {243--248}, + location = {Atlanta, GA, USA}, + doi = {http://doi.acm.org/10.1145/1450135.1450191}, + publisher = {ACM}, + address = {New York, NY, USA}, + } + +@article{TVLSI06, + author = {Cong, Jason and Han, Guoling and Zhang, Zhiru}, + title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors}, + journal = {IEEE Trans. Very Large Scale Integr. Syst.}, + volume = {14}, + number = {9}, + year = {2006}, + issn = {1063-8210}, + pages = {986--997}, + doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050}, + publisher = {IEEE Educational Activities Department}, + address = {Piscataway, NJ, USA}, +} + + +@Book{NIOS2, + title = {{Nios II Processor Reference Handbook}}, + publisher = {Altera}, + year = {2009}, +} + + +@inproceedings{ARC08, + author = {Galuzzi, Carlo and Bertels, Koen}, + title = {The Instruction-Set Extension Problem: A Survey}, + booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing}, + year = {2008}, + isbn = {978-3-540-78609-2}, + pages = {209--220}, + location = {London, UK}, + doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21}, + publisher = {Springer-Verlag}, + address = {Berlin, Heidelberg}, + } + +@inproceedings{CODES99, + author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent}, + title = {{A flexible code generation framework for the design of application specific programmable processors}}, + booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign}, + year = {1999}, + pages = {27--31}, + location = {Rome, Italy}, + publisher = {ACM}, + address = {New York, NY, USA}, + } + +@inproceedings{ASAP05, + author = {L'Hours, Ludovic}, + title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}}, + booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors}, + year = {2005}, + pages = {127--133}, + publisher = {IEEE Computer Society}, + address = {Washington, DC, USA}, +} +% Index: /anr/section-2.2.tex =================================================================== --- /anr/section-2.2.tex (revision 92) +++ /anr/section-2.2.tex (revision 93) @@ -60,6 +60,6 @@ CAIRN group at INRIA Bretagne Atlantique benefits from several years of expertise in the domain of retargetable compiler -(Armor/Calife\cite{FIXME:IRISA} since 1996, and the Gecos -compilers\cite{FIXME:IRISA} since 2002). +(Armor/Calife\cite{CODES99} since 1996, and the Gecos +compilers\cite{ASAP05} since 2002). %%% EXPERTISE DANS DES DOMAINES: LIP OK Compsys was founded in 2002 by several senior researchers with experience in Index: /anr/section-3.1.tex =================================================================== --- /anr/section-3.1.tex (revision 92) +++ /anr/section-3.1.tex (revision 93) @@ -119,6 +119,6 @@ difficult task, since it involves designing both a micro-architecture and a compiler for this architecture. Besides, to our knowledge, there is still -no available open-source design flow\footnote{There are commercial tools -such a } for ASIP design even if such a tool would be valuable in the +no available open-source design flow for ASIP design even if such a tool + would be valuable in the context of a System Level design exploration tool. \par @@ -128,5 +128,5 @@ only a small fraction of the architecture has to be specialized}, and help ASIP designers to focus on compilers, for which there are still many open -problems\cite{CODES04,FPGA08}. +problems\cite{ARC08}. This approach however has a strong weakness, since it also significantly reduces opportunities for achieving good seedups (most speedup remain between 1.5x and @@ -138,8 +138,8 @@ %performing efficient instruction selection and/or storage resource (register) %allocation \cite{FPGA08}). -To cope with this issue, recent approaches~\cite{DAC09,DAC08} advocate the use of +To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of micro-architectural ISE models in which the coupling between the processor micro-architecture and the ISE component is thightened up so as to allow the ISE to overcome the register -I/O limitations, however these approaches tackle the problem for a compiler/simulation +I/O limitations, however these approaches generally tackle the problem for a compiler/simulation point of view and not address the problem of generating synthesizable representations for these models. Index: /anr/task-3.tex =================================================================== --- /anr/task-3.tex (revision 92) +++ /anr/task-3.tex (revision 93) @@ -39,15 +39,20 @@ of the architecture, along with its architectural extensions \begin{livrable} - \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple extensible MIPS architectural template} - \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple extensible MIPS architectural template} - %\mustbecompleted{FIXME .....} + \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple MIPS } + { A SystemC simulation model for an simple extensible MIPS architectural template } + \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple MIPS} + {A synthesizable VHDL model for an simple extensible MIPS architectural template} \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0} - - \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a extensible MIPS with tight - architectural integration of its instruction set extensions} - \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a extensible MIPS with tight - architectural integration of its instruction set extensions} + { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being + already available from Altera}{0:0:0} + \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a complex-MIPS} + {A SystemC simulation model for a extensible MIPS with a tight architectural integration of + its instruction set extensions} + \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a complex-MIPS} + {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of + its instruction set extensions} \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0} - + {A evaluation report with quantitative analysis of the performance/area trade-off induced by + the different approaches} \end{livrable}