Changeset 94

Timestamp:

Feb 4, 2010, 7:20:02 PM (14 years ago)

Author:

coach

Message:

 

File:

• anr/section-2.2.tex (modified) (1 diff)

anr/section-2.2.tex

@@ -85 +85 @@
 description of an IP (coprocessor) from a sequential algorithm.
 \par
+
+%In multimedia applications, image processing is the major challenge embedded systems
+%have to face.  It is computationally intensive with power requirements to meet. Image
+%processing at pixel level, like image filtering, edge detection, pixel correlation or at 
+%bloc level such as motion estimation have to be accelerated. For that goal, 
+
+The ROMA project involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
+reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
+computing structure to computation patterns that can be speed-up and/or power efficient. 
+On the contrary of previous attempts  to design reconfigurable processors, which have 
+focused on the definition of complex interconnection network between simple operators, 
+the ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
+operators to avoid traditional overhead, in reconfigurable devices, related to 
+the interconnection network. 
 %%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
 %%% 2 IRISA ?