Index: /anr/task-3.tex
===================================================================
--- /anr/task-3.tex	(revision 94)
+++ /anr/task-3.tex	(revision 95)
@@ -23,10 +23,10 @@
 
     \begin{livrable}
-      \itemV{0}{18}{d}{\Sirisa}{Instruction selection for user defined custom instructions}
+      \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}{0:0:0}
         In this first version of the software, the computations patterns corresponding to
         custom instruction are specified by the user, and then automatically extracted (when
         beneficial) from the application intermediate representation. 
         %\mustbecompleted{FIXME .....}
-      \itemL{18}{24}{d}{\Sirisa}{Automatic extraction of patterns}{0:0:0}
+      \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{0:0:0}
         In this second version, the software will also be able to automatically identify 
         interesting pattern candidates in the application code, and use them as custom 
@@ -39,18 +39,18 @@
  of the architecture, along with its architectural extensions 
     \begin{livrable}
-      \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple MIPS } 
+      \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS }{1:.5:.5} 
       { A SystemC simulation model for an simple extensible MIPS architectural template }
-      \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple MIPS}
-      {A synthesizable VHDL model for an simple extensible MIPS architectural template}
-      \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0}
-	  { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
-	  already available from Altera}{0:0:0}
-      \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a complex-MIPS}
+      \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{0:0:0}
       {A SystemC simulation model for a extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a complex-MIPS}
+      \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{0:0:0}
+	  { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
+	  already available from Altera}
+      \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS}{1:.5:.5}
+      {A synthesizable VHDL model for an simple extensible MIPS architectural template}
+      \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{0:0:0}
       {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0}
+      \itemV{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:0}
       {A evaluation report with quantitative analysis of the performance/area trade-off induced by
       the different approaches}