Index: /anr/section-6.1.tex
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--- /anr/section-6.1.tex	(revision 95)
+++ /anr/section-6.1.tex	(revision 96)
@@ -1,4 +1,13 @@
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 \subsubsection{\irisa}
+
+The CAIRN group is an INRIA - Bretagne Atlantique project and a part of IRISA, UMR
+6074. CAIRN members are affiliated from University of Rennes\~1 or Ecole Normale 
+Supérieure de Cachan. the goal of CAIRN is to study reconfigurable system-on-chip, 
+i.e. hardware systems whose configuration may change before or even during execution. 
+To this end, CAIRN intends to approach reconfigurable architectures from three angles: 
+the invention of new reconfigurable platforms, the development of associated 
+transformation, compilation and synthesis tools, and the exploration of the interaction 
+between algorithms and architectures.
 
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@@ -20,5 +29,5 @@
 for integrated systems Architecture") is a public research laboratory
 sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
-Grenoble Institute of Technology (Grenoble-INP) and Université Joseph Fourier
+Grenoble Institute of Technology (Grenoble-INP) and Universitￜ Joseph Fourier
 (UJF).
 The research topics cover the specification, design, verification, test,
@@ -43,5 +52,5 @@
 de la Communication, et de la Connaissance), is a French CNRS laboratory 
 (UMR 3192) that gathers 4 research centers in the west and south 
-Brittany; from the Université de Bretagne-Sud (UBS), the Université de 
+Brittany; from the Universitￜ de Bretagne-Sud (UBS), the Universitￜ de 
 Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). 
 \\
@@ -84,5 +93,5 @@
 The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
 more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). 
-The « System on Chip » Department of LIP6 consists of  80 people, including 40 PHD students. 
+The ￜ System on Chip ￜ Department of LIP6 consists of  80 people, including 40 PHD students. 
 The research focus on CAD tools and methods for VLSI and System on Chip design. 
 \\