Index: anr/section-1.tex
===================================================================
--- anr/section-1.tex	(revision 89)
+++ anr/section-1.tex	(revision 97)
@@ -2,14 +2,14 @@
 The market of digital systems is about 4,600 M\$ today and is estimated to
 5,600 M\$ in 2012. However the ever growing applications complexity involves
-higher integration of heterogeneous technologies and requires the design of
+integration of heterogeneous technologies and requires the design of
 complex Multi-Processors System on Chip (MPSoC).
-During the last decade, the design of complex digital ASICs (Application Specific
+\par
+During the last decade, the design of ASICs (Application Specific
 Integrated Circuits) appeared to be more and more reserved to high volume markets, because
 the design and fabrication costs of such components exploded, due to increasing NRE (Non
 Recurring-Engineering) costs.
-\\
-FPGA (Field Programmable Gate Array) components, such as the
+Fortunately, FPGA (Field Programmable Gate Array) components, such as the
 Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
-implement a complete MPSoC with multiple processors and several
+implement a complete MPSoC with multiple processors and several dedicated
 coprocessors for a few keuros per device.
 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
@@ -20,25 +20,19 @@
 major companies to design innovative devices and to enter new, low and
 medium volume markets.
-\\
+\par
 The objective of COACH is to provide an integrated design flow, based on the
 SoCLib infrastructure~\cite{soclib}, and optimized for the design of
-multi-processors digital systems targetting FPGA devices.
+multi-processors digital systems targeting FPGA devices.
 Such digital systems are generally integrated
 into one or several chips, and there are two types of applications:
-It can be embedded (autonomous) applications
-such as personal digital assistants (PDA), ambiant computing components
+They can be embedded (autonomous) applications
+such as personal digital assistants (PDA), ambiant computing components,
 or wireless sensor networks (WSN)
 They can also be extension boards connected to a PC to accelerate a specific computation,
 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
-\\
-The COACH project fundamental issues are related to design methodologies
-for digital systems, providing estimation, exploration and design tools
-targeting both performance and power optimization at all the abstraction
-levels of the flow (system, architecture, algorithm and logic). 
-
+\par
 %verrous scientifiques et techniques
 \vspace*{.9ex}\par
-The COACH environment mixes and integrates several hardware and software technologies.
-The more important technologies are:
+The COACH environment will integrate several hardware and software technologies:
 \begin{description}
 \item[Design Space Exploration]
@@ -60,9 +54,10 @@
     The HLS tools of COACH will support a common language and coding style to avoid
     re-engineering by the designer.
-\item[Targeted hardware architecture and technology] 
+\item[Platform based design] 
     COACH will handle both \altera and \xilinx FPGA devices.
     COACH will define architectural templates that can be customized by adding
     dedicated coprocessors and ASIPs and by fixing template parameters such as
-    the number of CPU and the operating system.
+    the number of embedded processors or the number of sizes of embedde memory banks,
+    or the embedded the operating system.
     Basically, the 3 following architectural templates will be provided:
     \begin{enumerate}
@@ -76,9 +71,9 @@
     Moreover, the specification of the application will be independant of both the
     architectural template and the target FPGA device.
-\item[Communication interfaces]
-    Coach will define and implement an homogeneous HW/SW communication infrastructure and
-    communication APIs (Application Programming Interface).
-    These laters are on-chip communications between processors and coprocessors,
-    and external communications between the FPGA and the host PC. 
+\item[Hardware/Software communication middleware]
+    Coach will implement an homogeneous HW/SW communication infrastructure and
+    communication APIs (Application Programming Interface), that will be used for 
+    communications between software tasks running on embedded processors and 
+    dedicated hardware coprocessors,
 \end{description}
 The COACH design flow will be dedicated to system designers, and will as
@@ -99,8 +94,6 @@
 MPSoC architectures (\tima, \ubs, \upmc),
 ASIP architectures (\irisa),
-High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip).
+High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
 \\
-%The CoACH proposal can be described as an extension of the SoCLib virtual
-%prototyping platform to the FPGA technologies.
 The COACH project does not start from scratch.
 It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
@@ -115,34 +108,37 @@
 \par
 The COACH proposal has been prepared during one year by a technical working group
-involving all the academic partners (one monthly meeting from january 2009 to february
-2010). The objective of these meetings was to analyse the issues of integrating
-and enhancing the formers tools and tecnnologies into a unique framework allowing to both
-virtual prototyping and hardware generation.
+involving the 5 academic partners (one monthly meeting from january 2009 to february
+2010). The objective was to analyse the issues of integrating
+and enhancing the existing tools and tecnnologies into a unique framework.
+Most of the general software architecture of the proposed design flow (including the
+exchange format specification) has been define by this working group.
 Because the SocLib platform is the base of this project, it may be described as an
 extension of the SoCLib platform.
+
+%The main development steps of the COACH project are: 
+%\begin{enumerate}
+%   \item Definition of the end user inputs:
+%    The coarse grain parallelism of the application will be described as a communicating
+%    task graph, each task being described in C language.
+%    Similarly the architectural templates with their parameters and the design constraints
+%    will be specified.
+%  \item Definition of an internal format for representing task.
+%  \item Development of the GCC pluggin for generating the internal format of a
+%    C task.
+%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
+%    the internal format. This will allow to swap from one tool to another one, and to
+%    chain them if necessary.
+%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
+%    platform to generate the bitstream for the various FPGA families and architectural
+%    templates.
+%  \item Development of new tools such as ASIP compiler, HPC design environment and
+%    dynamic reconfiguration of FPGA devices.
+%\end{enumerate}
+
 \par
-The main development steps of the COACH project are: 
-\begin{enumerate}
-   \item Definition of the end user inputs:
-    The coarse grain parallelism of the application will be described as a communicating
-    task graph, each task being described in C language.
-    Similarly the architectural templates with their parameters and the design constraints
-    will be specified.
-  \item Definition of an internal format for representing task.
-  \item Development of the GCC pluggin for generating the internal format of a
-    C task.
-  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
-    the internal format. This will allow to swap from one tool to another one, and to
-    chain them if necessary.
-  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
-    platform to generate the bitstream for the various FPGA families and architectural
-    templates.
-  \item Development of new tools such as ASIP compiler, HPC design environment and
-    dynamic reconfiguration of FPGA devices.
-\end{enumerate}
-\par
-The two major FPGA companies \altera and \xilinx are participating in this
-project to support the partners providing the software technologies, and to
-help to generate efficient bitsream for both FPGA families.
+Two major FPGA companies are involved in the project : \xilinx will contribute
+as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
+providing documentation and development boards (\altera). These two companies are strongly motivated
+to help the COACH project to generate efficient bitsream for both FPGA families.
 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
 real use cases to benchmark the COACH design environment.
@@ -152,5 +148,6 @@
 The architectural templates, and the COACH software tools will be distributed under the
 GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
-IP core library) will be freely available for non commercial use. Commercial licences
-will be negociated for industrial exploitation.
+IP core library) will be freely available for non commercial use. For industrial exploitation
+the technology providers are ready to propose commercial licenses, directly to the end user,
+or through a third party.
 
