Index: anr/section-2.2.tex
===================================================================
--- anr/section-2.2.tex	(revision 94)
+++ anr/section-2.2.tex	(revision 97)
@@ -2,17 +2,18 @@
 % Relevance of the proposal 
 
-The COACH proposal addresses directly the Embedded Systems of
+The COACH proposal addresses directly the \emph{Embedded Systems} item of
 the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
-providing the industry the novel design capabilities enabling them to increase their
+providing SMEs novel design capabilities enabling them to increase their
 design productivity with design exploration and synthesis methods that are placed on top 
-of the state-of-the-art methods, and thus, allowing the industry to better cope with the 
-complexity of designed digital systems.
+of the state-of-the-art methods.
+This project proposes an open-source framework for mapping multi-tasks software applications
+on Field Programmable Gate Array circuits (FPGA).
+
 \par
-COACH will also contribute to the following strategic objectives of the ARPEGE program:
-COACH will specifically contribute to enable the building of open development and run-time
-environments for software and services, interoperable middleware and tools to support
+COACH will contribute to build an open development and run-time
+environment, including communication middleware and tools to support
 developers in the production of embedded software, through all phases of the software lifecycle,
 from requirements analysis until deployment and maintenance.
-\\
+
 More specifically, COACH focuses on:
 \begin{itemize}
@@ -25,4 +26,5 @@
 environment, suitable for co-operative and distributed development.
 \end{itemize}
+
 COACH outcome will contribute to strengthen Europe's competitive position by developing
 technologies and methodologies for product development, focusing (in compliance with the
@@ -31,30 +33,61 @@
 in COACH will enable new and emerging information technologies for the development,
 manufacturing and integration of devices and related software into end-products.
-\\
-This project proposes an open-source framework for architecture synthesis targeting 
-Field Programmable Gate Array circuits (FPGA).
+
 \par
-% LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
-To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
-\\ % LIEN AVEC AUTRES PROJETS: IRISA
-The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing 
-joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
+The COACH project will benefit from a number of previous projects:
+\begin{itemize}
+\item SOCLIB :
+The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories 
+and 6 industrial companies. 
+It supports system level virtual prototyping of shared memory, multi-processors
+architectures, and provides tools to map multi-tasks software application on these
+architectures, for reliable performance evaluation.
+The core  of this platform is a library of SystemC simulation models for 
+general purpose IP cores such as processors, buses, networks, memories, IO controller.
+The platform provides also embedded operating systems and software/hardware
+communication middleware.
+The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
+this project enhances SoCLib by providing the synthesisable VHDL models required
+for FPGA synthesis.
+\item ROMA :
+The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
+reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
+computing structure to computation patterns that can be speed-up and/or power efficient. 
+The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
+operators to avoid traditional overhead, in reconfigurable devices, related to 
+the interconnection network. 
+The project will  borrow from the ROMA ANR xxproject (2007-2009) and the ongoing 
+joint INRIA-STMicro Nano2012 project to adapt existing pattern
 extraction algorithms and datapath merging techniques to the synthesis of customized 
 ASIP processors.
-\par
+\item TSAR :
+The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a 
+scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
+plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL 
+models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
+\item BioWic
 On the HPC application side, we also hope to benefit from the experience in
 hardware acceleration of bioinformatic algorithms/workfows gathered by the
 CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
 be able to validate the framework on real-life HPC applications.
+\end{itemize}
+
+
 \par
-%%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK
-Regarding the expertise in  High Level Synthesis (HLS), the project
-leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project
-developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped
-in LIP6 and TIMA laboratories. \\
-Regarding architecture synthesis skills, the project is based on a know-how
-acquired over 10 years with the COSY European project (1998-2000) and the
-DISYDENT~\cite{disydent05} project developped in LIP6.\\
-%%% EXPERTISE DANS DES DOMAINES: IRISA OK
+The laboratories involved in the COACH project have a well estabished expertise
+in the following domains:
+\begin{itemize}
+\item 
+In the field of High Level Synthesis (HLS), the project
+leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
+developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped
+by the LIP6 and TIMA laboratories. 
+\item
+Regarding system level architecture, the project is based on the know-how
+acquired by the LIP6 and TIMA laboratories in the framework of various projects  
+(COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication 
+architectures for shared memory multi-processors systems.
+As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
+\item
 Regarding Application Specific Instruction Processor (ASIP) design, the
 CAIRN group at INRIA Bretagne Atlantique benefits from several years of
@@ -62,6 +95,7 @@
 (Armor/Calife\cite{CODES99} since 1996, and the Gecos
 compilers\cite{ASAP05} since 2002).
-%%% EXPERTISE DANS DES DOMAINES: LIP OK
-Compsys was founded in 2002 by several senior researchers with experience in
+\item
+In the field of compilers, the Compsys group was founded in 2002 
+by several senior researchers with experience in
 high performance computing and automatic parallelization. They have been
 among the initiators of the polyhedral model, a theory which serve to
@@ -69,51 +103,16 @@
 programs. It is expected that the techniques developped by Compsys for
 parallelism detection, scheduling, process construction and memory management
-will be very useful as a first step for a high-level synthesis tool.
+will be very useful as a Rfront end for the a high-level synthesis tools.
+\end{itemize}
+
 
 \par
-%%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK
-The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to
-describe hardware architectures with shared memory space and to deploy software
-applications on them to evaluate their performance. 
-The heart of this platform is a library containing simulation models (in SystemC)
-of hardware IP cores such as processors, buses, networks, memories, IO controller.
-The platform provides also embedded operating systems and software/hardware
-communication components useful to implement applications quickly.
-However, the synthesisable description of IPs have to be provided by users. \\
-This project enhances SoCLib by providing synthesisable VHDL of standard IPs.
-In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable 
-description of an IP (coprocessor) from a sequential algorithm.
-\par
-
-%In multimedia applications, image processing is the major challenge embedded systems
-%have to face.  It is computationally intensive with power requirements to meet. Image
-%processing at pixel level, like image filtering, edge detection, pixel correlation or at 
-%bloc level such as motion estimation have to be accelerated. For that goal, 
-
-The ROMA project involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
-reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
-computing structure to computation patterns that can be speed-up and/or power efficient. 
-On the contrary of previous attempts  to design reconfigurable processors, which have 
-focused on the definition of complex interconnection network between simple operators, 
-the ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
-operators to avoid traditional overhead, in reconfigurable devices, related to 
-the interconnection network. 
-%%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
-%%% 2 IRISA ?
-%%% 2 ASIP tool such as ... 
-%%% 2 ...
-%%% 2 Coach uses pattern extractions from ROMA
-\mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\}
-\par
 % FIXME A VERIFIER L'appel d'offre
-The different points proposed in this project cover priorities defined by the commission 
+Finally, it is worth to note that this project cover priorities defined by the commission 
 experts in the field of Information Technolgies Society (IST) for Embedded
-systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
+Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
 and allowing to apply efficiently applications and various products on embedded platforms,
 considering resources constraints (delais, power, memory, etc.), security and quality
 services$>>$.
-\\
-Our team aims at covering all the steps of the design flow of architecture synthesis.
-Our project overcomes the complexity of using various synthesis tools and description 
-languages required today to design architectures.
 
+
